Readers Speak Out on DSM: Part 2
			Jonah McLeod Our three-part report on readers' experiences with deep-submicron design continues. This installment focuses on design verification in general and offers strong opinions on formal verification in particular.
		Designers Gain When IP Vendors and Pure-Play Foundries Team Up
			by David Fung and S.Y. Tan-Stahel Developing libraries and other IP in parallel with bringing a fabrication process on line gives designers the flexibility to choose the foundry and the IP that best meet their specific needs.
		Concurrent Engineering Delivers at the Chip and System Level
			by John Lynch and Harold Schiefer Two design teams--at a system maker and a chip vendor--work together successfully while thousands of miles apart.
		Focus Report: Programmable Logic
			by Alexander Braun FPGAs and CPLDs ride finer process geometries, new architectures, and embedded functions to new capabilities, new markets.
		Editorial
			by Jonah McLeod Discovering a Reluctant New EDA Tool Vendor
		Viewpoint
			by John Birkner FPGAs Penetrate the Production-Volume Gate Array Market
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		Tools & Technologies