Streamlining HDL Code Coverage Analysis
			by Steve Forde, Steve Bishop, and Ramnath S. Velu The right code coverage tool and a new methodology helped designers verify nine unique ASICs thoroughly--and with fewer sleepless nights.
		A Virtual Test Revolution
			by James F. Boettcher and H. Glenn Carson, Jr. By making test debugging and verification more concurrent with the design process, virtual testing could dramatically reduce postsilicon test debugging time.
		Bringing up an ASIC Prototype
			by Kenneth Ngoc Nguyen and James M. Fenton With months of effort at stake, designers should keep in mind several guidelines to tame the chaos of the ASIC evaluation and characterization process.
		Focus Report: Programmable Logic
			by Gil Bassak Looking to lure designers with the promise of flexibility and fast turnaround, vendors have cooked up a virtual feast of programmable devices.
		Editorial
			by Jonah McLeod Free the PC!
		Viewpoint
			by Craig Siegel The True Value of Virtual Test Software
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