Coding RTL Verilog to Facilitate an Optimum
Verification Flow
By Harry Foster and Lionel Bening
Selecting and RTL verifiable subset and simple coding style maximizes performance of simulation, Boolean equivalence, and model checking, while enabling an optimal flow through synthesis and physical design.
Reconfigurable Prototyping Speeds Hardware/Software Integration
By Vince Dugar, Ben Baron, and Randy Fout
By integrating all aspects of a new tape drive design before fabricating ASICs, the design team saved time and produced code that worked nearly flawlessly on the final hardware.
Focus Report:
Web-based Design
By Peggy Aycinena
Oh what a tangle the Web creates, when the design team remotely collaborates
Optimizing a Compute Farm with LSF
By Ron Ranauro
A
load-sharing facility can help to weed out some of the thornier problems that crop up in compute farming.
