Managing Noise on the K6-III
By Ted Williams and Luke Tsai
Shrinking line widths demand attention to noise issues, so design methodologies must change to include comprehensive noise analysis.
Promoting Design Reuse in Large
Corporations
By Robert Quinn
High-level behavorial modeling can speed a design along the road to tapeout by identifying architectural opportunities and pitfalls.
Integrated TV-On-Silicon Package Requires Parallel Developments
By Chris Hopwood, Peter Hawkins, Andrew Vagg, and John Somberg
The reduction in components required by next-generation analog television receivers demanded a radical approach. A
two-chip, two-process implementation in a single package delivered the goods.
Enhancing Test Coverage at the Register Transfer Level
By Eric Hoang, Jamie Fontenot, Kuang-Hsien Chen
RTL buffer insertion and fault grading help to identify untested functions and low-fault coverage areas where added test vectors can be generated.
Focus Report: RTL Floorplanners
By Mike Maisen
Movin' on up. Like the Jeffersons, floorplanning functions are moving into logic design, system design, and beyond.
Editorial
By Tets Maniwa
Future IC Design Will Need
a New Design Perspective
