Evaluating ASIC Memory Trade-offs
			by Mark Buchanan On-chip memory and a small cache can increase performance when you're using an embedded RISC core.
		Design Methodology for Quickly and Accurately Generating SRAMs
			by Lee Tavrow, John Johnson, and Mark Santoro Created to reduce design time, guarantee completely correct behavior at first tape-out and provide process retargetability, a small company devises its own optimized flow combining standard and custom tools and methods.
		Designers Tackle the Testability of a System-Level IC
			by Ki Joo Jeong, Srini Krishnaswami, Bejoy G. Oomman, and Shankar Hemmady To test and debug a 400,000-gate system on silicon with embedded processor, memory, PCI interface, and peripheral control logic, three different test strategies were needed.
		Focus Report: High-Speed ASIC Benchmark
			by R.T. "Tets" Maniwa The effect of interconnect delays on deep-submicron designs forces designers to look beyond speed as the primary indication of circuit performance.
		Editorial
			by Jonah McLeod Embedded DRAMs Ride the Confluence of Technologies.
		Viewpoint
			by Zhihong Liu Hot Carrier Effect--A Fading Concern or a Growing Problem?
		In The News
		Tools & Technologies