Developing a Design Methodology for Embedded
Memories
By Eric Hall and George Costakis
Embedding custom memories into fast and small microprocessors demands a design methodology that encompasses the entire design flow and takes into account such challenges as timing, electromigration, and embedded test.
Promoting Design Reuse in Large Corporations
By Thomas Harms
One mega-corporation is promoting design reuse across the board by establishing a centralized EDA organization for encouraging close collaboration and the development of reuse standards.
Reconfigurable Computing Accelerates Verification
By Eric Shieh
A small
consulting firm used reconfigurable computing coprocessor technology and its attendant software to speed the verification of a large networking device.
Focus Report: Physical Verification
By Tets Maniwa
The task of confirming the physical design increases in importance and complexity as processes move to 0.18µm, where a mask set can cost over $250,000.
EDA Platform Benchmark: The Desktop FPGA Design Flow
By James Lee and Bob Peterson
The course of FPGA production runs smooth indeed - as long as your machine contains enough memory, you can turn out a synthesized and routed FPGA in less than a day.
Editorial
By Tets Maniwa
Polishing Up the Crystal Ball
Roadmap Throws EDA a Few Curves
By Steve Schulz
EDA vendors must
take dramatic steps forward to keep up with the predicted trends in design size, speed, and power consumption.
Viewpoint
By Mark-Eric Jones
Performance Can Help To Manage IC Complexity
