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Emulation Technology for ASIC Core Verification
By Alan Singletary
Emulation strategies vary across three ASIC cores.


A Standard IP Interface for Custom SOC Designs
By Suresh Dholakia
Design mandates integration across system blocks and interconnects.

Rdram Modeling Issues and Challenges
By Scott Taylor and Nicolas Jamba
Modern processor design demands more than just a good model.

Hierarchal ASIC Design at Three Million Gates and Above
By Toshio Aizawa and Ravi Thummarukudy
DSM processes demand physical & logical design - in that order.

Predicting Semiconductor Failure Modes
By Venkataraman Lakshiminarayanan
It's a jungle out there for electronic devices.

Focus Report: ASICs Today
By Tets Maniwa

Editorial
By Tets Maniwa
Hail and Farewell

Technology Bits
By London Jin
Don't Abuse Fault Coverage

Viewpoint
By Srinath Ananthraraman
Project Leaders Must Focus on Team Productivity


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