High-Speed State Machine Design
			by Stephen L. Wasson Three methods can be used to describe state flows. While each has its own list of pros and cons, a composite method could provide the answer.
		Co-Verification Strategies In Hardware-Software Co-Design
			by Steven E. Schulz The need for co-verification of both hardware and software forces many hard choices for system designers who desire a smooth path to silicon (and code).
		Focus Report: Processor Cores, Megacells, and Complex Functions
			by R.T. "Tets" Maniwa System-level integration circuit design requires reusable libraries of functions.
		FPGAs Can Meet ASIC Design Requirements
			by Tim Saxe In the future, FPGAs will have to become more "gate array-like" to allow the use of EDA tools
		Product Evaluation: Workstation-Based VHDL Simulators
			by Larry Saunders and Yatin Trivedi Larry Saunders and Yatin Trivedi evaluate three VHDL simulators in this, their fourth EDA product evaluation for Integrated System Design
		Editorial
			by Jonah McLeod Will Datapath Compilation Be the Next Hit EDA Tool?
		Programmable Notes
			by Larry Waller Hooray or Ho-Hum?
		EDA Consumer Advocate Diary: Verilog Won and VHDL Lost?
			by John Cooley Verilog Won and VHDL Lost? You Be the Judge.
		Viewpoint
			by John Cooper IC Signal Crafting: the Key to Successful Interconnect Design
		In The News
		Tools & Technologies