Solutions for H/W S/W Co-Design
			by Anne Hilow and Jim Morizio The increasing design complexity of a system on a chip requires software to be integrated into the design flow.
		3-D Parasitic Extraction for Deep Submicron IC Design
			by Wayne Dai and Waikai Sun Advances in process technologies have increased the requirements for a more complete analysis of interconnect characteristics.
		Top-Down Timing Design
			by Bryan Hoyer and Donna Mitchell Upfront timing analysis reduces timing errors and leads to thoroughly optimized designs.
		Focus Report: CMOS ASICs
			by R.T. "Tets" Maniwa CMOS ASICs continue to provide designers with an increasing range of capabilities at the cost of design complexity.
		Editorial
			by Jonah McLeod Capturing the Intellectual Assets of Human Beings Is a Good Thing, Right?
		Viewpoint
			by Marty Walker Breaking the Interconnect Barrier
		In The News
		Tools & Technologies