Tell Me Again--What Does the "S" in SOC Stand For?
			by Takashi Hasegawa and John McNally Because sequenital steps in designing SOCs often occur simultaneously or with many iterations, codesign can rapidly turn into chaos without clear flow and the software to keep it all under control.
		Making the ASIC/FPGA Decision
			by Rockland K. Awalt FPGAs offer an ever more competitive technology as processes and time to market continue to shrink--even in the face of the ongoing move from schematic design to HDLs.
		Hardware-Software Codesign of an Image Processing Unit
			by Clarisse Adida, Michel Boubal, Xavier Granger, Philippe Lamaty, and Jean-Pierre Moreau A codesign tool suite helped handle the demands of hardware-software codesign by facilitating architectural exploration, partitioning, scheduling, and interface synthesis.
		Focus Report: Design-for-Test Tools
			by Peggy Aycinena Design-for-test tools are available in an array of sizes and colors, but not everybody is buying the latest or greatest.
		EDA Platform benchmark: Place and Route
			by James Lee and Peggy Aycinena The Windows NT platform continues to perform in an EDA environment, this time handling the key place-and-route phase with ease.
		Editorial
			by Tets Maniwa What Does Design Reuse Take?
		Inside VHDL
			by Arkadi Poliakov and Anatoli Sokhatski Developing VITAL-Compliant VHDL Models
		Tools
			by Tets Maniwa Putting Pspice to the Test
		Viewpoint
			by Michael Kaskowitz Don't Forget the Software
		In The News

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