Deep-submicron Timing Closure By Steve Schulz New and highly anticipated tool flows will only succeed in melding logic and physical design if they resolve the critical-path timing problems currently plaguing DSM design.

Evaluating ASIC Reuse By Mike Augarten Monitoring various design metrics helps one company to allocate necessary resources to various phases of the development process. Challenges of Mixed-signal Design By Vlad Bril and Nilesh Amin Combining the skill sets and IP of two complementary organizations leads to successful and timely design outcomes. The Armor of IP Verification By Richard Ellis, Neil Bray, and David Chaplin Verifying a design in two HDLs? Just one of several challenges encountered in IP verification Speech Recognition SOC through Architectural Synthesis By Remco de Zwart, Roel Janssen, Andre Pool, and Cees Heikamp A C-based design flow assisted with synthesis for this SOC Focus Report: Design Entry and Encapsulation By Peggy Aycinena

Editorial By Tets Maniwa Sea Change or Old Faithful Inside EDA By Kat Hsu Internet Tools for Managing the Development Supply Chain Viewpoint By Karen Bartleson Courage to Change the Standard

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