Kicking out the Clock By Steve Furber Recent advances in self-timed design have led to renewed industrial interest in a methodology to enable the full potential of system-on-a-chip technology.

Prototyping Self-time Circuits using PLDs By Simon Moore PLDS present an interesting test case for illustrating the vlaue of self-timed circuit design. Boosting Performance with Resolution Enhancement Technology By Christopher Spence Device geometries are shrinking faster than current lithography wavelengths should permit. Designers have several tools at hand to ease the pain. ASIC Block Based Design Methodology for Fine-Grained FPGA's By Hicham Belhadj and Paresh Patel The migration of ASIC design flows is feeding the demand for FPGA-type designs. The Art of Architectural Exploration By Dale E. Hocevar System-level design is requiring enhanced modeling techniques to lend needed efficiencies to the development cycle. Focus Report: Synthesis By Mike Maisen Physical synthesis, hybrid ASIC/FPGA devices, and language concerns—synthesis users have a lot to consider.

Editorial By Tets Maniwa EDA versus Dot.com Business Inside IP By Martin S. Won Enabling the Next Generation of Platform-based Design Viewpoint By Jim Turley OEMs Should Retain Ownership and Control for Custom Silicon IP

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