An Alphabet Soup of Memory by R.T. "Tets" Maniwa Memory is more and more becoming a critical issue, and there is a plethora of acronymic devices on the market and in the wings. Here we take a look at the special function memory devices and their primary characteristics.
		Using Timing Analysis for ASIC Sign-Off
			by Paul Granese Static timing analysis can improve timing verification in ASIC design and produces results much more quickly.
		Resurgence in Prototyping
			by Joel Woodward With complex ICs, the real time-killer is verification, not design. But are there methodologies to make the process easier?
		Focus Report: Physical Design Tools
			by R.T. "Tets" Maniwa In this focus report, we identify the features and capabilities in physical design tools necessary to achieve working silicon in deep submicron ASIC designs.
		Fixing Some Glitches is All in the Timing
			by Michael J. Peters Undetected output signal glitches can cause quality and yield problems.
		Editorial
			by Jonah McLeod Coping with Integrated Circuit Complexity
		Programmable Notes
			by Larry Waller Where Does the Fitter Deal Fit?
		Inside HDL
			by Larry Saunders and Yatin Trivedi Testbench Tutorial, Part II
		Viewpoint
			by Gary Kennedy Customer Service in the Semiconductor Business
		In The News
		Tools & Technologies