Automating Cost-Effective Library Creation By David Pietromonaco Creating custom libraries will give chip designers multiple advantages in the coming era.

Tackling Functional Verification for Virtual Components By Tom Anderson and Robin Bhagat VSIA is hard at work defining the deliverables needed to succeed with design reuse. A Common Reuse Strategy for ASICs and FPGAs By Carol Fields New FPGA architectures are enhancing system-level integration and ASIC compatible tools. FPGA to ASIC Migration By Marc Royer and Mark Goode Changing an FPGA into a replacement ASIC can be rewarding if you're looking to save money. Europe 2000 By Peggy Aycinena The Design & Reuse Center Focus Report: System Design Tools By Steven E. Schulz Attending to Signal Integrity in Complex Designs By Tets Maniwa Signal integrity issues in ASIC design refuse to be ignored.

The Embedded Microprocessor Report By Tets Maniwa Here's a paper debate on the characteristics of current generation microprocessors.

Editorial By Peggy Aycinena Is There a Prima Donna in the House? Inside IP By Paul Fillinich and Sherri Davis Mining for intellectual property within the organization Viewpoint By Sang Wang A New Breed: Hierarchal Verification Tools

Advertiser Index In the News Feedback

Send electronic versions of press releases to news@isdmag.com
For more information about isdmag.com e-mail webmaster@isdmag.com
Comments on our editorial are welcome.
Copyright © 2000 Integrated System Design Magazine