Readers Speak Out on Deep Submicron
			Jonah McLeod Integrated System Design surveys its readers and gets several earfuls. Our report covers the need for an RTL interoperability standard, floorplanning, and placement and routing.
		Property Verification Using Theorem Proving and Model Checking
			by Ying Xu, Eduard Cerny, Allan Silburt, and Roger B. Hughes Designers try out two tools on an experimental high-speed 16 x 16 ATM switch fabric containing about 5 million transistors.
		Deep-Submicron Designs Require Netlist Reduction for Fast Simulation
			by Jack S. Thomas, Amod Kale, and You-Peng Wei Hitachi uses a new tool to reduce cache memory megacell netlists to a manageable size.
		Focus Report: Design Verification
			by R.T. "Tets" Maniwa Test tools have boosted their capabilities in response to today's needs.
		Editorial
			by Jonah McLeod The Foundry Business Is Booming, but Will the Good Times Last?
		Viewpoint
			by Anand Naidu For Soft Cores, You Need More than Synthesizable HDL Code
		In The News
		Tools & Technologies
		Feedback