Design Plan Synthesis Refines
Multimillion-Transistor Designs
By Jacob Greidinger
Complex IC design poses a serious question: what's the best way to handle the block-level interconnect when the designers finally stitch the blocks together? One answer lies in
a new methodology called "design plan synthesis."
DSP Architectures Reach for Greater Parallelism
By Emmanuel Roy and David Crawford
Meeting the demand for hi-speed and sophisticated digital signal processors will require clever coding, advanced compilers, and increasingly complex component constructs.
Test Benches in C Speed Verification by Unifying Emulation and Simulation
By Marty
Newman
Software designers have long used simple measurement systems to help them work more efficiently. Hardware designers can use these same techniques to streamline their design processes and facilitate code reuse.
Handling Multiple Clock Domains in Scan Design
By Samy Makar
Many of today's complex chips include multiple clock domains. Knowing how to identify and correct any problems that occur in the scan chains
within these clocks is essential.
Focus Report: EDA on the PC
By Jeffrey Erickson
Windows NT versus Linux, Episode Three. But is it The Phantom Menace or The Empire Strikes Back?
Editorial
By Tets Maniwa
The Quality of EDA Tools is Strained
Noise
By Tets Maniwa
Logic and Noise in High-Speed Designs
Viewpoint
By Dale Pollek
Get By with a Little Help from Your Friends
