Developing a Strategy for IP Evaluation By Tim Daniels To reduce risk, development teams should utilize cores created with many of the same disciplines and rules employed in ASIC design.

Deep-Submicron System-on-a-chip Designs By Robin C. Sarma and Arjun Rajagopal Power grid verification is becoming an imperative in deep-submicron design. Special Feature: Europe 2000 By Sean Dean The Alba Centre Timing Closure in DSM Design By Ravishankar Arunachalam and Larry Pileggi Can we continue to predict timing of ICs prior to manufacturing as technolgoies continue to scale? Useful Design-for-test Practices By Paul Yohannes Successful DFT for deep-submicron system-on-a-chip ASIC designs requires attention to detail from specification all the way through tape-out. Focus Report: PLD Tools By Peggy Aycinena

Editorial By Peggy Aycinena From the Four Corners of the Earth Inside EDA By Tapan A. Mehta Essential Elements of a Successful Intellectual Property Evaluation Viewpoint By Steve Carlson The Verification Cycle: A Breakthrough is Needed

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