Automating MOTIVE
			by Luke L. Chang Developing an analysis environment for automatic static timing analysis using Quad Design's MOTIVE.
		Timing Binds EDA Tools to Foundry
			by Jonah McLeod The interplay between design, layout, and process affects system-on-a-chip designs.
		Reliability Management for Deep Submicron ICs
			by Riko Radojcic The demands of time-to-market collide with the requirements for long-term reliability studies.
		Implementing PCI in an FPGA
			by Mike Dini Flexibility and predictability are key elements in choosing an FPGA for a PCI interface.
		Focus Report: Design for Test Tools
			by R.T. "Tets" Maniwa Test development times grow with IC complexity, However, these tools may take some of the worries out of your design.
		Optimizing Layout on High-Speed Digital Printed Circuit Boards
			by Heinz Jakibczuk Applying new physical design synthesis tools reduces PCB design cycles by nearly 30 percent.
		Editorial
			by Jonah McLeod To Own or to Lease: for IC Companies. That is the Question
		Programmable Notes
			by Larry Waller Shrink-Wrap PLD Design Tools?
		Viewpoint
			by Maqsoodul Mannan Future Directions for the Verilog Language
		In The News
		Tools & Technologies