Coverification Tames Cache and Bus Interface Controller Design
			by Steven P. Larky The highly complex interfaces in today's designs require significant attention to the verification flow. A hardware-software coverification environment allows more thorough verification.
		Focus Report: Synthesis
			by Gil Bassak The crucial role of synthesis is being complicated by among other things, the growing dominance of interconnect lenth in signal delays.
		EDA Platform Benchmark: Simulation II
			by James Lee and Bob Peterson This set of benchmarks revises the first set using a more accurate method of calculating time and also throw 400-MHz PCs into the mix.
		Linux Has What It Takes for EDA
			by James Lee Linux is arguably the better mousetrap for engineering applications. Why haven't EDA vendors beaten a path to its door?
		Benchmark Feedback
		Editorial
			by Jonah McLeod Who's Got the Power?
		Toolbox
			by Tets Maniwa Test-Driving the Newest version of Modelsim PE/Plus
		Viewpoint
			by Rod Dudzinski Topology before Synthesis
		Feedback
		In The News