Alternatives to CMOS Processes Promise High Speeds--At a Price By Tets Maniwa Though CMOS processes have yet to reach their size of performance limits, alternative processes have already carved niche markets for themselves and appear poised to make some inroads into the mass markets.

Designing Connected Information Devices Using Programmable Logic By Stephen J. Fricke A veteran of the design wars gives a personal view of his migration from ABEL and schematics to VHDL modules for FPGA design development. Design-for-Test Streamlines the Design of a Graphics Accelerator By Mehran Amerian A graphics chip vendor used a DFT methodology and an optimized tool suite to speed the testing of a complex accelerator from design, through tapeout, to manufacturing. Testing System Chips: Methodologies and Experiences By Sujit Dey, Yervant Zorlan, and Erik Jan Marinissen Advances in semiconductor process and design technology require new strategies for testing complex system chips. Focus Report: Design Verification By Peggy Aycinena That's verification spelled with an "I" for integration and interoperability--but is this wise? System-level design verification has its day in the sun as a logistical quagmire.

Editorial By Tets Maniwa I Know What We Did This Summer DAC Review By Steven E. Schulz What Really Happened at DAC? Viewpoint By Michael (Mac) T.Y. McNamara Coverage Doesn't Have To Be A Dead-End Street

Feedback In The News Tools and Technology

Send electronic versions of press releases to news@isdmag.com
For more information about isdmag.com e-mail webmaster@isdmag.com
Comments on our editorial are welcome.
Copyright © 2000 Integrated System Design Magazine