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Technical Papers Spotlight

Open Standards and Product Differentiation

System-Level and Application Specific ESD Protection Guide

Dangers of Aftermarket Counterfeit Battery Packs

Leveraging ADC Technology to Capture, Compute, and Communicate in Microcontroller-Based Embedded Systems

Addressing the Complexity of "Smart" Devices Through Low Power Hierarchical Design

Accelerating, Analyzing, and Securing Network Traffic

Build, Borrow, Buy: New Approaches to Addressing Software Complexity

Integrated ZigBee Radio Implementation and Testing

Fundamentals of a Mixed Domain Oscilloscope

Coherent Optical Signal Generation with High-Performance AWG

Radar Processing: FPGAs or GPUs?

High Performance Embedded Computing and Its Impact on Mil/Aero Applications

Improve Quality and Decrease Time to Market with Better Requirements Management

Why Honest Weigh Scales Are Application Specific

Protecting People, Data, and Revenue with Security-Optimized Embedded Designs: Part 2

Linux System/User Space Virtualization for Next Generation Real-time Embedded Applications

Designing High-Efficiency LED Driver Circuits Using the NCL30051

Enhanced, High-Efficiency Power Factor Controller

Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms

Merging High-Performance Instruments and FPGAs for Best-in-Class WLAN Measurements

Technical Papers

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Tech Paper Title	Type	Date
Analyzing and Debugging Performance Issues with complex ARM CoreLink System IP Components Cadence Design Systems, ARM	White Paper	3/12/2013
20nm Design--How this Advanced Technology Will Transform SoCs and EDA Cadence Design Systems	White Paper	7/1/2011
Improving Verification Productivity through Adopting Dynamic Load and Reseed Methodology Cadence Design Systems	White Paper	6/1/2011
ASIC Prototyping Simplified Cadence Design Systems	White Paper	3/1/2011
Silicon Realization--A New Approach to Faster, Better and More Profitable Silicon Cadence Design Systems	White Paper	10/22/2010
Closing the Gaps to Electronics Success through Comprehensive Co-Design Cadence Design Systems	White Paper	10/1/2010
EDA360: The Way Forward for Electronic Design Cadence Design Systems	White Paper	4/27/2010
Eliminating Routing Congestion Issues with Logic Synthesis Cadence Design Systems	White Paper	8/6/2009
Closing the Chip Architecture Implementation Feedback Loop Cadence Design Systems	Technical Paper	8/6/2009
TLM-driven Design and Verification--Time for a Methodology Shift Cadence Design Systems	White Paper	6/1/2009
Power Integrity: Effective management of timing, power, and signal integrity Cadence Design Systems	White Paper	3/17/2009
Implementing a Low-Power Reference Flow for an Advanced Microprocessor Cadence Design Systems, ARM	Vault	6/11/2008
Model-Based Methods Critical for Effective Manufacturing-Aware Physical Design Cadence Design Systems	White Paper	3/18/2008
Next-Generation Signoff Analysis Tackles Electrical, Physical, and Manufacturing Challenges Cadence Design Systems	White Paper	1/16/2008
Chip Design Using 45nm Processes Requires a Holistic Approach to Planning and Implementation Cadence Design Systems	White Paper	1/16/2008

1 - 15 of 48 > Next 15

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All papers are reviewed by EE Times staff. If approved for posting, we'll send you a link as to where the paper can be found on the site. All papers must be technical in nature; Press releases, Product announcements, PowerPoint presentations, pamphlets, incomplete documents/abstracts will not be accepted. For more information, contact Emily Soucy.