Education & Training

Technical Papers Spotlight

Open Standards and Product Differentiation

System-Level and Application Specific ESD Protection Guide

Dangers of Aftermarket Counterfeit Battery Packs

Leveraging ADC Technology to Capture, Compute, and Communicate in Microcontroller-Based Embedded Systems

Addressing the Complexity of "Smart" Devices Through Low Power Hierarchical Design

Accelerating, Analyzing, and Securing Network Traffic

Build, Borrow, Buy: New Approaches to Addressing Software Complexity

Integrated ZigBee Radio Implementation and Testing

Fundamentals of a Mixed Domain Oscilloscope

Coherent Optical Signal Generation with High-Performance AWG

Radar Processing: FPGAs or GPUs?

High Performance Embedded Computing and Its Impact on Mil/Aero Applications

Improve Quality and Decrease Time to Market with Better Requirements Management

Why Honest Weigh Scales Are Application Specific

Protecting People, Data, and Revenue with Security-Optimized Embedded Designs: Part 2

Linux System/User Space Virtualization for Next Generation Real-time Embedded Applications

Designing High-Efficiency LED Driver Circuits Using the NCL30051

Enhanced, High-Efficiency Power Factor Controller

Using Plots for HDL Debugging as a Powerful Alternative to Traditional Waveforms

Merging High-Performance Instruments and FPGAs for Best-in-Class WLAN Measurements

Technical Papers

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Tech Paper Title	Type	Date
Comprehensive Verification of ARM Processor-Based SoC Designs Cadence Design Systems, ARM	Vault	12/13/2007
Signal Integrity Issues When Embedding Analog Blocks Cadence Design Systems	Conference Paper	10/18/2007
Encounter Express: Simplifying ARM Cortex-A8 Implementation Cadence Design Systems, ARM	Vault	4/13/2007
Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits Cadence Design Systems	White Paper	2/20/2007
Silicon Design Chain Extends Low-Power Design Collaboration Cadence Design Systems, ARM	Vault	11/15/2006
Reducing Block, Chip, and System Design Risk with a "Plan-to-Closure" Verification Approach Cadence Design Systems	White Paper	10/27/2006
Speeding Design of Custom Silicon: The Virtuoso Custom Platform Cadence Design Systems	White Paper	9/21/2006
Hardware and Software Verification for ARM SoC Design Cadence Design Systems	Conference Paper	6/6/2006
Silicon Design Chain Extends Low-Power Design Collaboration Cadence Design Systems, ARM	Vault	6/2/2006
Motivations and Methodology for Nanometer Library Characterization Cadence Design Systems	Technology Paper	8/26/2005
It Takes an Industry: A Low-Power Design-through-manufacturing Flow Cadence Design Systems, ARM	Vault	8/4/2005
Accelerating ARM Core-based Wireless Application Development Cadence Design Systems, ARM	Vault	3/15/2005
Complex SoC Verification Designed for Reuse Cadence Design Systems, ARM	Vault	2/11/2005
Parallel Software Development with Simulation Tools for MXC Architectures Freescale Semiconductor, Cadence Design Systems, ARM, Virtio	Vault	2/10/2005
Compliance and Validation of the AMBA On-Chip Bus Standard Cadence Design Systems, ARM	Vault	1/28/2005

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All papers are reviewed by EE Times staff. If approved for posting, we'll send you a link as to where the paper can be found on the site. All papers must be technical in nature; Press releases, Product announcements, PowerPoint presentations, pamphlets, incomplete documents/abstracts will not be accepted. For more information, contact Emily Soucy.