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Tech Paper Title Type Date
SoC Efficient Simulation Using Dynamic Power Management
Freescale Semiconductor
White Paper 7/9/2012
A Systematic Approach to Tester Pattern Generation and Stabilization for SoC
Freescale Semiconductor
White Paper 6/29/2012
SoC Testbench Compliance
Freescale Semiconductor
White Paper 6/14/2012
Noise Aware Obstructions in Hierarchically Partitioned Designs
Freescale Semiconductor
White Paper 6/5/2012
QorIQ DPAA Primer for Software Architecture
Freescale Semiconductor
Application Note 6/1/2012
WELL Isolation Methodology for Power Domain Independent Implementation
Freescale Semiconductor
White Paper 5/31/2012
A Hybrid interconnect approach for GALS NoC systems
Freescale Semiconductor
White Paper 4/29/2012
Frequency Search Algorithm for Non-Linear Trim for RC Oscillators
Freescale Semiconductor
White Paper 4/12/2012
An Overview of Methods for Increased Gate Level Compilation Efficiency
Freescale Semiconductor
White Paper 4/8/2012
Mathematics for smart power grid design
Freescale Semiconductor
White Paper 4/1/2012
The "Mini" Read 6T Memory Cell Concept
Freescale Semiconductor
White Paper 4/1/2012
Improving IC Silicon Yields by Voltage Drop Based Timing Closure
Freescale Semiconductor
White Paper 4/1/2012
Smart Spare Cell Distribution
Freescale Semiconductor
White Paper 4/1/2012
Aspect Ratio Driven Floorplan for IR Drop and Die Size Reduction
Freescale Semiconductor
White Paper 4/1/2012
Efficient Redundancy Management for Die Area Reduction
Freescale Semiconductor
White Paper 3/26/2012

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All papers are reviewed by EE Times staff.  If approved for posting, we'll send you a link as to where the paper can be found on the site.  All papers must be technical in nature; Press releases, Product announcements, PowerPoint presentations, pamphlets, incomplete documents/abstracts will not be accepted. For more information, contact Emily Soucy.