FPGA Technology at the pointy end of the spear
1/10/2011 8:27 PM EST
LC tank circuit
Once the interconnect is compensated, the fundamental limits to the BER in the physical layer are set by the random jitter in the transceivers. To achieve a 1 sigma random jitter rate below 1 psec, requires a new clock recovery and PLL approach. The stability of a conventional voltage controlled ring oscillator is not enough. Altera developed an LC tank circuit with the dynamic range of a voltage controlled ring oscillator and the stability and high queue of an LC filter. This leverages the latest 28 nm CMOS process technology from TMSC.
"One of the biggest challenges our customers face is productivity," Jiva said. "We've looked at how we can reduce their bring-up and debug time." As an example of one challenge, Jiva mentions the problem of actually measuring what the receiver sees after all the clock recovery, CTLE and DFE equalization. No physical instrument can probe this signal without grossly distorting it. The solution is ODI: on-die instrumentation.
"More and more of the IP is on the receiver side- the clock recovery, CTLE and DFE," Li said. "You don't have observability from an external view. How do you non-invasively probe what is going on inside the chip?" Li, who was the CTO with Wavecrest before joining Altera, went on to say, "We wanted to put a big instrument in a tiny box inside the chip, with orders of magnitude lower cost and power."
The result is the EYEQ Eye Viewer, a technique of monitoring the actual eye diagram after the receiver equalization and clock recovery. It's like having a sampling scope on the die. And, with the use of onboard software controlling the transmitter, on die instrumentation can be turned into a bit error rate tester.
"The end customer can bring up a board much faster with this feature. At 10 Gbps and beyond, there is no other way," Jiva added.
Li pointed out another very suitable and potentially important feature with the EYEQ. Rarely is the eye symmetric at these high data rates in excess of 10 Gbps. If you know what the eye looks likes, you can adjust the position of the sample and hold time and voltage to where the eye opening is largest, rather than in the center of the eye. "This can sometimes dramatically reduce the BER, with no hardware changes at all," Li adds.
While some of these technologies are leveraged in high speed ASICs, Jiva says that especially in the high end Ethernet product space, the short product development cycle time and last minute flexibility of an FPGA is an important asset. Specs at the high end are evolving. "An FPGA can integrate the latest specs in its design, while the specs must be frozen as much as a year in advance to be implemented in an ASIC."
These advances in silicon capabilities to overcome the limitations of the copper based interconnects are extending the life of conventional circuit board technology into the next generation.