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iniewski
I am Canadian, and never heard of Bit Error Ratio...always Bit Error ...
Frank Eory
Since you mentioned Nortel, I'm guessing you're Canadian and I think "bit error ...
FPGA Technology at the pointy end of the spear
Eric Bogatin
1/10/2011 8:27 PM EST
LC tank circuit
Once the interconnect is compensated, the fundamental limits to the BER in the physical layer are set by the random jitter in the transceivers. To achieve a 1 sigma random jitter rate below 1 psec, requires a new clock recovery and PLL approach. The stability of a conventional voltage controlled ring oscillator is not enough. Altera developed an LC tank circuit with the dynamic range of a voltage controlled ring oscillator and the stability and high queue of an LC filter. This leverages the latest 28 nm CMOS process technology from TMSC.
"One of the biggest challenges our customers face is productivity," Jiva said. "We've looked at how we can reduce their bring-up and debug time." As an example of one challenge, Jiva mentions the problem of actually measuring what the receiver sees after all the clock recovery, CTLE and DFE equalization. No physical instrument can probe this signal without grossly distorting it. The solution is ODI: on-die instrumentation.
"More and more of the IP is on the receiver side- the clock recovery, CTLE and DFE," Li said. "You don't have observability from an external view. How do you non-invasively probe what is going on inside the chip?" Li, who was the CTO with Wavecrest before joining Altera, went on to say, "We wanted to put a big instrument in a tiny box inside the chip, with orders of magnitude lower cost and power."
The result is the EYEQ Eye Viewer, a technique of monitoring the actual eye diagram after the receiver equalization and clock recovery. It's like having a sampling scope on the die. And, with the use of onboard software controlling the transmitter, on die instrumentation can be turned into a bit error rate tester.
"The end customer can bring up a board much faster with this feature. At 10 Gbps and beyond, there is no other way," Jiva added.
Li pointed out another very suitable and potentially important feature with the EYEQ. Rarely is the eye symmetric at these high data rates in excess of 10 Gbps. If you know what the eye looks likes, you can adjust the position of the sample and hold time and voltage to where the eye opening is largest, rather than in the center of the eye. "This can sometimes dramatically reduce the BER, with no hardware changes at all," Li adds.
While some of these technologies are leveraged in high speed ASICs, Jiva says that especially in the high end Ethernet product space, the short product development cycle time and last minute flexibility of an FPGA is an important asset. Specs at the high end are evolving. "An FPGA can integrate the latest specs in its design, while the specs must be frozen as much as a year in advance to be implemented in an ASIC."
These advances in silicon capabilities to overcome the limitations of the copper based interconnects are extending the life of conventional circuit board technology into the next generation.
Once the interconnect is compensated, the fundamental limits to the BER in the physical layer are set by the random jitter in the transceivers. To achieve a 1 sigma random jitter rate below 1 psec, requires a new clock recovery and PLL approach. The stability of a conventional voltage controlled ring oscillator is not enough. Altera developed an LC tank circuit with the dynamic range of a voltage controlled ring oscillator and the stability and high queue of an LC filter. This leverages the latest 28 nm CMOS process technology from TMSC.
"One of the biggest challenges our customers face is productivity," Jiva said. "We've looked at how we can reduce their bring-up and debug time." As an example of one challenge, Jiva mentions the problem of actually measuring what the receiver sees after all the clock recovery, CTLE and DFE equalization. No physical instrument can probe this signal without grossly distorting it. The solution is ODI: on-die instrumentation.
"More and more of the IP is on the receiver side- the clock recovery, CTLE and DFE," Li said. "You don't have observability from an external view. How do you non-invasively probe what is going on inside the chip?" Li, who was the CTO with Wavecrest before joining Altera, went on to say, "We wanted to put a big instrument in a tiny box inside the chip, with orders of magnitude lower cost and power."
The result is the EYEQ Eye Viewer, a technique of monitoring the actual eye diagram after the receiver equalization and clock recovery. It's like having a sampling scope on the die. And, with the use of onboard software controlling the transmitter, on die instrumentation can be turned into a bit error rate tester.
"The end customer can bring up a board much faster with this feature. At 10 Gbps and beyond, there is no other way," Jiva added.
Li pointed out another very suitable and potentially important feature with the EYEQ. Rarely is the eye symmetric at these high data rates in excess of 10 Gbps. If you know what the eye looks likes, you can adjust the position of the sample and hold time and voltage to where the eye opening is largest, rather than in the center of the eye. "This can sometimes dramatically reduce the BER, with no hardware changes at all," Li adds.
While some of these technologies are leveraged in high speed ASICs, Jiva says that especially in the high end Ethernet product space, the short product development cycle time and last minute flexibility of an FPGA is an important asset. Specs at the high end are evolving. "An FPGA can integrate the latest specs in its design, while the specs must be frozen as much as a year in advance to be implemented in an ASIC."
These advances in silicon capabilities to overcome the limitations of the copper based interconnects are extending the life of conventional circuit board technology into the next generation.
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iniewski
1/11/2011 12:10 PM EST
Eric, I take an issue with your statement: "A typical product spec is to have no errors in the received data during the life of the product. If the lifetime is 5 years, and the data rate is 28 Gbps, the bit error rate (BER) must be less than 10-18". I have worked on developments of high-speed serial links for several years. BER of 1E-15 was sometimes expected but 1E-12 was fine in many cases. I rarely heard of 1E-18, that is insane to test. And saying that a typical product will have no errors ever is just not realistic...Kris
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bogatin
1/11/2011 3:24 PM EST
I think the goal of many comm systems is to deliver a quality of service with no errors in the lifetime of the product. Of course, it is impossible for the physical layer to provide this, let alone, as you suggest, to test it. This is why there is an overhead in the data transmitted for error correction.
A BER in the phy layer of 10^-12 in a 20 Gbps link will be an error once a minute or so. It would not work without error correction. I should have been more clear that I was referring to the system BER, not the phy layer BER.
thanks for the clarification.
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zeeglen
1/11/2011 1:17 PM EST
"high queue of an LC filter" ???
A "high queue" is a line-up of rock-concert attendees smoking illicit substances.
The LC filter and/or tank is "High Q", where "Q" stands for "Quality factor"
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bogatin
1/11/2011 3:24 PM EST
Zeeglen- you are absolutely correct. I got carried away with my trying to spell out terms. It should be hi Q, as you state. Thanks for the correction!
--eric
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zeeglen
1/11/2011 7:13 PM EST
Noticed something else same paragraph that is of interest. Does Altera need an external copper inductor or is the L part of the internal silicon?
The use of an LC tank in a VCO for PLL clock recovery is not new, was a conventional method long before the rickety voltage controlled ring oscillator was ever used. But if the L has been incorporated into the silicon then yes, that is relatively new. If so, might you have a link to Atera publications describing this technique in more detail?
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iniewski
1/11/2011 8:51 PM EST
To @zeeglen, on-chip inductors have been widely used in high-speed and RF circuits for several years now...Kris
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zeeglen
1/11/2011 10:11 PM EST
Thanks, have not used RF chips with oscillators lately. The last one was a few years ago still used a ring oscillator. I am guessing that inductors are formed on one or more metal layers?
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David Ashton
1/11/2011 9:03 PM EST
Fascinating stuff to those of us who are not on the cutting edge. I remember eye patterns from 50 baud FSK systems and 9600 BPS Codex modems. (God, I sound like a real old fart....) As data rates got faster they seemed to be done away with. Nice to see them still being used at 10 GHz. I always reckoned they were immensely valuable, you could see from the pattern exactly what was wrong with your link.
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zeeglen
1/11/2011 10:20 PM EST
Eye patterns are useful at any data rate, but it takes familiarity and experience to interpret them. I remember a meeting where a young guy just out of school claimed that one could not simply glance at an eye pattern and classify it as good, acceptable, or bad. I had to set him straight that maybe kids fresh out of school could not, but those who have looked at eye patterns for 30 years certainly can.
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elPresidente
1/13/2011 5:38 AM EST
It's Bit Error RATIO, not Bit Error Rate.
Li is waving the pom poms again, clumsily using ex-CTO credentials to claim "putting a big instrument in a tiny box inside the chip", when Nortel was shipping this BER enhancing eye profiling technology in multi-gigabit chips in the early 1990's based on Tremblay et al's US patent 4,823,360 (1988), followed by NEC, Cisco, JDS, Vitesse, and others with patents in the same area. The eye asymmetries owing to the nature of fiber optics AFEs seems to also be a revelation for Li, but is day to day life for the customers he probably has never been in the lab with. [yawn]
@zeeglen - chip inductors have been used or on-chip oscillators for over two decades. In 28nm, they'll take up a huge amount of chip area in terms of transistor count. You are also FOS, and the kid was right, about seeing eye-closing phase hits that happen once in tens of minutes if not hours.
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Frank Eory
1/14/2011 12:25 PM EST
Since you mentioned Nortel, I'm guessing you're Canadian and I think "bit error ratio" must be a Canadian thing. In 25 years of comms engineering in the U.S., I have always heard BER defined as "bit error rate."
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iniewski
1/14/2011 1:19 PM EST
I am Canadian, and never heard of Bit Error Ratio...always Bit Error Rate...maybe I am loosing my Canadian ties, eh? ;-)...Kris
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KB3001
1/14/2011 6:02 AM EST
High speed serial links alongside a reconfigurable fabric have indeed been one of FPGAs' USPs recently. FPGAs continue to eat in to the ASICs' market....
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iniewski
1/14/2011 11:15 AM EST
True KB3001, FPGAs continue to eat into the ASIC market but the reason has to do mostly with cost of designing ASIC going thru the roof not with high speed links technology. Ten years ago I worked on ASICs with 2.5-10 Gb/s IOs while FPGAs at the time could deliver 1 Gb/s so there was a gap. But that gap still exists, FPGAs can do 10 Gb/s while highly specialized ASICs can do 100 Gb/s (the number above are per differential pair, you can always increase the bandwidth by going more parallel). One can of course argue that 10 Gb/s per 2 pins is sufficient so that gap is less relevant and FPGA is on par. ASIC development cost however used to be in single millions of dollars, is now is several millions of dollars so TAM required to justify the cost exists only in very small number of system level sockets. Hence everyone is using FPGAs unless it is a cell phone, PC or Ethernet switch...Kris
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