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Robotics Developer
I too share the concerns of a number of these posts. I wonder how the US can ...
iniewski
And attempting to answer Junko's question: semiconductor processes are not ...
Fabless follow-up
Don Scansen
12/1/2010 8:25 PM EST
In my last Dew Point column I lamented the fabless approach to the chip business. Questioning the widely accepted outsourcing model attracted several reader comments. Anyone interested in the topic may be interested to look at those reader comments as they are insightful and a few offer some additional historical perspective. At least there was one comment that can be spun to appear to agree with my commentary: "The semiconductor industry was way more fun back in the 1980s, when dinosaurs like Jerry Sanders still roamed."
Dylan McGrath commented that the fabless model has been an unqualified success. But perhaps I was not quite getting to the heart of the matter as much as other commentators.
Bolaji Ojo wrote a recent piece on the outsourcing craze and where it has left us, warning us to Stop Gorging on China. There's more to the China story than just cheap labor. China's control of rare earth metals moved Toshiba to enter into talks with the Mongolian government to develop new sources for these critical materials.
As for IC production, it also made good business sense to shift to the pure play foundries in Asia, and the foundries in Taiwan got started at just the right time. Dennard's scaling model worked well, and the performance of new generations of CMOS devices was predictable. There was an opportunity to take mature, stable processes near the end of the learning curve and squeeze out any unnecessary costs. Chip companies began to see process technology less as a differentiator and more as a huge expense line. TSMC offered a flexible manufacturing option and continued to grow and invest in more capacity. The pure play foundries started to invest in research and development eventually moving closer to the leading edge of technology. Their growth to prominence took place before physical scaling for device performance was replaced with strain and other materials engineering. By the time gate length scaling was no longer able to keep transistor performance on track, TSMC was an industrial giant able to develop its own new technology strategies and was already emerging onto the forefront of industry research.
Staying competitive in semiconductor manufacturing today requires intensive research efforts into materials that can outperform silicon in planar technology platforms and eventually a replacement for planar devices. Today's contract wafer manufacturer does a lot more than take an existing recipe and apply operational efficiencies to reduce costs. Moving production to Asia, however inevitable it was, meant the loss of re-investment in North America for research and development. Perhaps Globalfoundries will bring some of that production, ecosystem and R&D back to the U.S. The bigger question is probably how long it can keep it there.
Speaking of advanced technology development, the International Electron Devices Meeting is less than a week away. Each year, I like to preview this IEEE conference since it is a leading forum for semiconductor technology. After revisiting the "Real Men" column, I am out of space for a complete rundown of the sessions. I intend to highlight more papers in the days ahead, but for now, let's stick to the theme.
Part of the motivation for writing about the fabless model was the belief that a tighter bond between circuit designers and manufacturing becomes more important with every new node. Whether those functions are engineering teams under the same corporate banner of an IDM or through vendor partnerships, it's a fact. And that was the motivation for IEDM creating a special session in 2007 that invited members of the design community to give their view of process technology development. That session continues this year. The emphasis of the 2010 edition, Session 17 – Confluence of Technology and Design, is "Challenges for Non-Conventional Devices and 3D LSIs."
With the exception of session chair Kazunari Ishimaru of Toshiba, there are no fabless chip companies, foundries, or even IDMs represented. All the authors are from academia. The abstract of one paper does claim collaboration with IBM, however. Thermal-Aware Design of 3D ICs with Inter-Tier Liquid Cooling is from D. Atienza of the Embedded Systems Laboratory at EPFL. As much as we hear about through-silicon via and 3D IC, this research on microfluidic channels for chip cooling will not spawn any consumer products for a very long time. Session 17 may boast the catchiest title of the conference, May the Fourth (Terminal) Be With You - Circuit Design Beyond FinFET, is a paper by H. Koike and co-authors from Japan's National Institute of Advanced Industrial Science and Technology (AIST). But getting down to the annual business of choosing some talks to attend (if you are lucky enough to be attending IEDM), this session boasts one industry guru that I would like to hear from. H.-S. Philip Wong of IBM fame and now at Stanford has contributed Device and Circuit Interactive Design and Optimization Beyond the Conventional Scaling Era.
Finally, I should note that even the IEDM program shows the broad acceptance of the fabless business model. Qualcomm, the poster child of the movement, will be represented by James Clifford, Senior VP and General Manager of Operations at the IEDM Luncheon on Tuesday, December 7.
Dylan McGrath commented that the fabless model has been an unqualified success. But perhaps I was not quite getting to the heart of the matter as much as other commentators.
Bolaji Ojo wrote a recent piece on the outsourcing craze and where it has left us, warning us to Stop Gorging on China. There's more to the China story than just cheap labor. China's control of rare earth metals moved Toshiba to enter into talks with the Mongolian government to develop new sources for these critical materials.
As for IC production, it also made good business sense to shift to the pure play foundries in Asia, and the foundries in Taiwan got started at just the right time. Dennard's scaling model worked well, and the performance of new generations of CMOS devices was predictable. There was an opportunity to take mature, stable processes near the end of the learning curve and squeeze out any unnecessary costs. Chip companies began to see process technology less as a differentiator and more as a huge expense line. TSMC offered a flexible manufacturing option and continued to grow and invest in more capacity. The pure play foundries started to invest in research and development eventually moving closer to the leading edge of technology. Their growth to prominence took place before physical scaling for device performance was replaced with strain and other materials engineering. By the time gate length scaling was no longer able to keep transistor performance on track, TSMC was an industrial giant able to develop its own new technology strategies and was already emerging onto the forefront of industry research.
Staying competitive in semiconductor manufacturing today requires intensive research efforts into materials that can outperform silicon in planar technology platforms and eventually a replacement for planar devices. Today's contract wafer manufacturer does a lot more than take an existing recipe and apply operational efficiencies to reduce costs. Moving production to Asia, however inevitable it was, meant the loss of re-investment in North America for research and development. Perhaps Globalfoundries will bring some of that production, ecosystem and R&D back to the U.S. The bigger question is probably how long it can keep it there.
Speaking of advanced technology development, the International Electron Devices Meeting is less than a week away. Each year, I like to preview this IEEE conference since it is a leading forum for semiconductor technology. After revisiting the "Real Men" column, I am out of space for a complete rundown of the sessions. I intend to highlight more papers in the days ahead, but for now, let's stick to the theme.
Part of the motivation for writing about the fabless model was the belief that a tighter bond between circuit designers and manufacturing becomes more important with every new node. Whether those functions are engineering teams under the same corporate banner of an IDM or through vendor partnerships, it's a fact. And that was the motivation for IEDM creating a special session in 2007 that invited members of the design community to give their view of process technology development. That session continues this year. The emphasis of the 2010 edition, Session 17 – Confluence of Technology and Design, is "Challenges for Non-Conventional Devices and 3D LSIs."
With the exception of session chair Kazunari Ishimaru of Toshiba, there are no fabless chip companies, foundries, or even IDMs represented. All the authors are from academia. The abstract of one paper does claim collaboration with IBM, however. Thermal-Aware Design of 3D ICs with Inter-Tier Liquid Cooling is from D. Atienza of the Embedded Systems Laboratory at EPFL. As much as we hear about through-silicon via and 3D IC, this research on microfluidic channels for chip cooling will not spawn any consumer products for a very long time. Session 17 may boast the catchiest title of the conference, May the Fourth (Terminal) Be With You - Circuit Design Beyond FinFET, is a paper by H. Koike and co-authors from Japan's National Institute of Advanced Industrial Science and Technology (AIST). But getting down to the annual business of choosing some talks to attend (if you are lucky enough to be attending IEDM), this session boasts one industry guru that I would like to hear from. H.-S. Philip Wong of IBM fame and now at Stanford has contributed Device and Circuit Interactive Design and Optimization Beyond the Conventional Scaling Era.
Finally, I should note that even the IEDM program shows the broad acceptance of the fabless business model. Qualcomm, the poster child of the movement, will be represented by James Clifford, Senior VP and General Manager of Operations at the IEDM Luncheon on Tuesday, December 7.
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junko.yoshida
12/3/2010 5:51 AM EST
As Don Scansen states in his column here, I think the heart of the matter is this: As a tighter bond between circuit designers and manufacturing becomes more necessary and important at every new node, what impact will it have on those of you who don't have fabs? Do we just leave things to the academia to solve the hard problems and hope for the best? How do you plan to innovate your next chips?
Could anyone explain that?
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dylan.mcgrath
12/3/2010 1:43 PM EST
Is there any scenario under which a significant number of U.S. chip companies will take back control of their manufacturing and return to building mega fabs in the U.S.? I honestly can't image it happening, except if there were some type of cataclysmic event...
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phoenixdave
12/3/2010 2:16 PM EST
I think Junko makes a very good observation with the question "How do you plan to innovate your next chips?" A lot of innovation comes out of production. New intellectual property is formulated based upon challenges with utilization and manufacturing, including within design and development. How to you remain innovative and obtain intellectual property value through utilization of your patented inventions if you have no control over the manufacturing processes?
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junko.yoshida
12/3/2010 3:11 PM EST
Thanks for articulating my question, phoenixdave.
That's exactly what I mean.
I do understand the business need for a lot of semi companies to go fab-lite.
But, here, I am not talking about "mega fabs." I want to know how tighter a linkage between the process technology and the next-gen chip design will be needed.
Or, are we saying that the semconductor design/manufacturing is a "matured" technology so that we don't really need to invest in the next-node material/production/process R&D, and let the academia and someone else in Asia worry about that?
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kdboyce
12/6/2010 2:35 AM EST
Fab-less or not, either situation can be a double edged sword.
For those who control their own fabs and production facilities, and who also can afford to maintain their own process development programs, unique products can be made and sold for high margins. The trick is keeping up with your competition who has the same capabilities. That takes a lot of money, which you have to earn by having a high "hit rate" on successful products. Under-utilized fabs are a huge $$$ drain.
On the other hand, depending solely upon one or more non-owned fabs and mfg/test facilities can allow you to pick and choose the best available for your product....unless you have some special requirements. Your infra-structure costs are a lot lower.
I have worked in both situations, and I have to say that I prefer a company with a fab.
In the fab-less case, our leading edge product was "leaked" to another fab with even less scruples who proceeded to copy it and sell thru a related company at much lower price. Law suits and ITU sanctions ultimately did not make up for the losses incurred. In another case, production capacity was suddenly restricted as the fab decided that its capacity should be shifted to another company's "hot" chip...which (understandably) earned them more money.
You are not in control of your destiny if you are fab-less.
Of course you can screw up your destiny fast if you cannot fully utilize and support the necessary fab activities to keep your products innovative and competitive.
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iniewski
12/7/2010 6:46 PM EST
Fabless or not? I guess the old questions remains...I would argue that tighter links between design and fab are needed from IC design technical point of view as we move down the path of shrinking processing nodes...but the business reality seems to be that smaller number of companies can afford the modern fab so the number of have-fabs is shrinking...I agree with @kdboyce, it is better to have a fab, but you need deep pickets...in some ways it is like saying that we all would like to be wealthy, healthy and handsome ;-)...Kris
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iniewski
12/7/2010 6:53 PM EST
And attempting to answer Junko's question: semiconductor processes are not mature, they change from generation to generation...I think semi process R&D can be effectively done only by those who have fabs (or perhaps a few leading academic centers sponsored by the same companies)...academia is better off by innovating at smaller, nanotechnology scale, where inventing new concepts by manipulating atoms, molecules, nano materials, etc is much more exciting...Kris
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Robotics Developer
12/7/2010 9:56 PM EST
I too share the concerns of a number of these posts. I wonder how the US can innovate with the fabs offshore. I have spent almost 20 years in the ASIC business and can say it is all about understanding the process and the process variations. To have cutting edge performance the designer must understand the process in significant detail with proper models for simulation and EDA tools that properly mate with the fab models / process parameters. It was always a challenge when trying to extract the most performance out of a process even with almost unrestricted access to the process details. I can't imagine how open the fabs would be to just any design team / EDA tool vendor but I wonder if it would be enough??? I have seen companies struggle and programs falter when the specter of Allocation of some critical part or needed component. Is it possible that designs now do not need to extract the most performance out of the process? It seems that designers face the prospect of "me too" ICs with a common fab/process. Not sure that is the best way to build market share or differentiation.
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