EDA DesignLine Blog
Time heals all wounds, and missteps?
nic mokhoff
6/23/2009 11:46 AM EDT
That's the grim news from Silicon Valley where EE Times editor at large Rick Merritt filed this story.
Increasingly only the few big chip makers will be able to afford to design big SoCs: Tape out costs can run as high as $20 million, but they are dwarfed by verification costs that can soar five times as high, according to venture capitalist Andy Rappoport, who contends that the payroll for verification teams alone can cost $2 million a month and silicon support teams to serve a couple OEM customers can run another million per month.
Mark Stevens, a principal at Sequoia Capital has been studying a model used in the biotech industry. Big companies help fund startups and once their products are ready to go they buy up the companies outright in what amounts to pre-arranged marriages.
I wonder if this model can be applied to large EDA companies. That is, fund a startup, and then buy it out. Has it been done before?
Some out of the box thinking needs to be contemplated. The EDA industry is hurting and nimble new players need to give the large players a run for their money.
One such company might be around the corner.
Oasys Design Systems, coming out of stealth mode after Independence Day, is claiming to reinvent RTL synthesis for chips beyond 20-million gates. The company has assembled a board of diectors that includes Joe Costello, former CEO of Cadence Design Systems, Sanjiv Kaul, former Sr. VP and GM of Synopsys, and Larry Yoshida, former CEO of Innotech and Tokyo Electron.
"When I learned of the Oasys approach to a significant problem, I saw real invention again. I had to get involved," is the story line offered by Costello who once expressed his angst about VCs and EDA.
Time will tell.
