Predictions for 2012: Tools

A couple of weeks ago I sent out a call for predictions related to EDA, IP and semiconductor industry companies. I received 24 predictions from 11 companies and I would like to thank all of them and the PR people who worked so hard to get them to me. I have divided the predictions into a number of categories: those related to industry trends, tools, ESL, IP and physical. As for myself, I will follow the Chinese proverb: a wise man once said nothing.

Earlier this week I presented the industry trends. You can find those here. Today I turn my attention to tools and while we can expect some of these to be a little self-serving, or at least wishful thinking, I think it demonstrates where the companies are prepared to spend their R&D dollars.

Michiel Ligthart Chief Operating Officer Verific Design Automation
Do-It-Yourself EDA Flows Take Off in 2012
When Verific started providing (System)Verilog and VHDL parsers in 2001, EDA companies were quick to jump on the bandwagon. Semiconductor companies with internal CAD teams and FPGA companies supporting customer design tools followed suit when they realized that they would be better off re-using Verific’s parsers than build their own. In 2012, semiconductor and system design houses without in-house EDA development will build one-of-a-kind EDA tools specific to their environment.  With the recent availability of a Perl API to SystemVerilog and VHDL front-ends, designers have access to an IEEE-compliant parser with no C++ knowledge required. Building your own SystemVerilog design gadget will become a trend in 2012.

Lauro Rizzatti General Manager of EVE-USA
Emulation Assumes Universal Verification Tool Title in 2012
Emulation will be awarded the title of universal verification tool in 2012.  Offering rigorous debugging capabilities and operating at multiple orders of magnitude faster than the venerable logic simulator, emulators have been accepted as a mandatory part of the verification tool flow.  Emulators can test designs of any type, and from any market segment, and are especially useful as software content and design complexity increase.  As one of the most versatile tools in the verification tool box, emulators validate and co-verify hardware and software on billion-gate devices by exercising billions of clock cycles, giving developers confidence in their design before committing it to silicon.

Mentor Emulation
Emulation Market to Grow by 18 Percent
Most established EDA technologies aren’t growing, but emulation is a clear exception to that rule. According to research by Gary Smith EDA (released in September 2011), the emulation market will almost double between 2009 and 2012, growing by 18 percent in 2012 alone. There are three primary reasons for this: existing emulation users need bigger emulators; new customers have discovered they can’t do without it; and as designs grow, it becomes onerous to build FPGA prototypes within project schedules.

Adnan Hamid Chief Executive Officer Breker Verification Systems
SoC functional verification will become a dominant topic in EDA.
Verification is already one of the most time-consuming activities in chip design. The explosive demand for mobile computing and communications devices is driving rapid growth in SoC design. The SoC  verification problem is much tougher due to the presence of embedded processors that are software-driven. The conventional transactional verification approach is not sufficient for SoC system-level testing and verification engineers are left with the time-consuming task of developing hand-written tests. Lacking an automated solution and under schedule pressure, these manual tests can only address the proverbial "tip of the iceberg" of system verification. In 2012, there will be much discussion in the industry on a new solution that automates SoC verification so that full system-level verification can be achieved.

Bill Neifert Chief Technology Officer Carbon Design Systems
Software will play an even larger part in the overall system design process
OK, there’s not much of a revelation here, but it’s striking how software is being used not only to drive high-level decisions in advanced SoC design but also low level ones as well.  More and more design teams are using software to make critical decisions, typically the exclusive domain of hardware designers and architects.  Software will take on a more important role in chip verification and power analysis as more and more backend processes are removed from the serial design flow and addressed earlier in the design process.

Ken Karnofsky, senior strategist for signal processing applications, MathWorks
Increased usage of FPGA-based applications
My prediction is a continuation of a recent trend toward well-integrated design and prototyping solutions for FPGA-based applications.  FPGAs are an attractive platform for many high-performance applications such as software-defined radio, computer vision, and high-speed motor control.  However, as noted in recent analysis by BDTI, FPGA complexity makes the development cost too high for many embedded application developers.  Advances in system-level design environments, automatic code generations, and prototyping hardware have chipped away at this problem, but have yet to coalesce into complete design, verification, and real-time testing solutions that make FPGAs accessible to a broad range of system and embedded engineers.  These solutions have begun to emerge, and in 2012, we will see new offerings that will accelerate this trend.

Bill Neifert Chief Technology Officer Carbon Design Systems
Cloud computing will make significant inroads for EDA tool execution
Cloud computing has seemed like a natural execution platform for many EDA tasks, especially in the verification space.  It’s not unusual for larger companies to run thousands of simulations as part of their regression testing process.  Today, most of that testing is done on internal farms of machines that must then be maintained and updated.  Companies have rejected the cloud in the past due to concerns about security and control.  These objections are the same ones that kept them from outsourcing work to India and China decades ago.  Eventually, economic forces win out and we’ve already seen this start to happen for cloud computing.

Adnan Hamid Chief Executive Officer Breker Verification Systems
The proliferation of SoCs and the need for system-level verification will drive the industry to adopt scenario model-based verification.
The explosion of new SoC devices that contain multiple blocks, IP elements and embedded processors yield complex systems that require verification of the entire SoC, not just individual elements.  Unfortunately, existing verification solutions are not readily adaptable or usable to accomplish this. A new approach based on "scenario modeling" is increasingly being used by verification engineers to achieve system-level SoC functional verification. Scenario modeling starts by specifying the desired outcome and then using automation techniques to generate the stimulus (software) required to achieve the outcome and compare the system response to the expected response. In 2012, the term "scenario model" will become familiar to teams tasked with verifying complex SoCs.

Mentor PCB
Virtual Prototyping becoming embedded into flows
We see the trend to more virtual prototyping throughout the electronic product design process accelerating. As electronic products get more compact, faster, hotter, etc., and companies have to meet aggressive time-to-market schedules, they can no longer afford to produce multiple physical prototypes and lab test them for all aspects of performance and reliability. Interconnect signal integrity, power distribution network integrity, heat management at the component, sub-system (PCB) and full system levels, vibration and shock, etc. all have to be thoroughly analyzed during the design process. This also requires close collaboration between design domains like electrical, mechanical and manufacturing. Editor’s note: This one could have equally fit in the ESL category, which I think is interesting.


Brian Bailey – keeping you covered

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