EDA/IP Weekly Roundup – Jan 25th

1/25/2012 10:40 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Mentor Graphics has announced that Fujitsu Semiconductor Limited has expanded its use of the Calibre® platform, incorporating the latest Calibre physical verification and design for manufacturing (DFM) capabilities in its design enabling flow for all Fujitsu Semiconductor projects, including its most advanced analog and digital designs. New Calibre productivity features include pattern matching for fast identification of litho hotspots and other design rule check (DRC) violations, automatic waivers for managing rule waivers during DRC, programmable electrical rule checking (PERC) for reliability verification, and the SmartFill function to realize advanced timing-aware filling for DFM.

A joint development between Packet Plus and Dini Group provides tools for networking designs at the earliest stage of the verification process. The new P+™ 1000 embedded packet debugger from Packet Plus provides the ability to control and interact with networking designs. Packet Plus used a Dini Group development board to represent the customer's target design in their development process. The Dini Group developed an interface card between their development boards and the P+ 1000 product. The P+ 1000 offers packet-by-packet control, an ability to work at any layer of the protocol stack, symbolic editing, and packet injection. The P+ 1000 also provides an approach to working with security protocols including at speed encryption/decryption, and key management.

Synopsys has announced that it has closed the acquisition of ExpertIO, Inc., an independent provider of verification IP (VIP) for industry standard protocols. Synopsys hopes that the addition of ExpertIO's team of protocol experts and its portfolio of storage VIP will accelerate their delivery of a broad line-up of high-performance, easy-to-use, full-featured VIP that can help designers address their growing verification challenges. The terms of the deal have not been disclosed. VIP provides functional models of on- and off-chip protocols that verification engineers use to test all of the interfaces on an SoC before manufacturing. It enables the engineer to verify how an interface conforms to published standards and also allows the engineer to verify the interactions among various interfaces on an SoC. 

Carbon Design Systems™ has announced that it closed calendar year 2011, recording its fifth consecutive year of growth driven by its leading virtual prototyping solutions for architects and firmware teams using the ARM® Cortex™ intellectual property (IP) family. Rapid adoption of advanced IP, such as the ARM Cortex A15, Cortex R5, Cortex A7, and Cortex A9, has increased demand for Carbon‘s 100% accurate system-level models for these platforms from Carbon IP Exchange, a web-based model portal.  In 2011, Carbon IP Exchange grew to more than 400 registered users who have downloaded more than 2,500 models for virtual prototyping of their SoC designs.

Arteris has announced that it has finished the twelve months of 2011 with an accounting profit based on strong revenue growth. Arteris' growth in 2011 was driven by increasing semiconductor vendor adoption of Arteris® FlexNoC®, the company's second-generation network on chip IP platform, and interchip link IP products. IP licensees in 2011 grew from 18 at beginning of the year to 39 at year end -- an addition of 21 new licensees and more than 100% growth. Reorders from existing licensees remained strong with approximately 60% of bookings coming from existing customers and approximately 40% coming from new licensees. In 2011, there were 45 new SoC projects started with the Arteris interconnect IP products. Multiple end products shipped in 2011, with Arteris-connected SoCs in systems such as smartphones, tablets, televisions, LCD projectors and automobiles.