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Frank Eory
This is an excellent summary of the methods most commonly used to minimize ...
Power 104: Reducing power consumption
Brian Bailey
4/16/2012 10:38 AM EDT
As we have already seen, power reduction is necessary in both the dynamic and static areas, especially for products where extended battery life is necessary. While improvements in the fabrication processes can have a large impact, these are the not the kinds of optimization available to engineers trying to create a design (aside from picking a low power technology). In this blog, we will concentrate on the general techniques available.
One thing to note is that power optimization is different from the other design optimization, such as area and timing. They are absolutes and while latencies may be dependent on application usage, the maximum clock frequency that a design can operate at is dictated by the slowest path in the design. Dynamic power is application dependent. I found this great example in a paper written by Anantha P. Chandrakasan and Robert W. Brodersen from University of California at Berkeley. They say:
An important attribute which can be used in circuit and architectural optimization, is the correlation which can exist between values of a temporal sequence of data, since switching should decrease if the data is slowly changing (highly correlated). An example of the difference in the number of transitions which can be obtained for a highly correlated data stream (human speech) versus random data is shown in Figure 1 - the transition activity for a few registers in an FIR filter design. For an architecture which does not destroy the data correlation, the speech data switches 80% less capacitance than the random input. In addition, the sequencing of operations can result in large variations of the switching activity due to these temporal correlations.
This can have a big impact on power estimation and in the optimization that may be applicable. For the types of optimization that can be considered I turn to Arvind Shanmugavel Director of Applications Engineering Apache Design, Inc. He lists:
Active power:
The following techniques are used to minimize active power consumption:
Static power:
The following techniques are used to minimize static power consumption:
Shawn McCloud, VP Marketing at Calypto Design Systems adds: a 2012 survey we just completed asked this very question. 68% of respondents cited clock gating as the most common method used to reduce power followed by power gating at 35%.
References
Anantha P. Chandrakasan and Robert W. Brodersen. Minimizing Power Consumption in CMOS Circuits. http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/418/paper.fm.pdf
Other parts of this series include:
If you spot an error, would like to propose an improvement or addition to this entry, or anything within this power archive, please let me know by sending me an email. Your comments will be added, and your name will be preserved in the document indicating your participation in its improvement.
Go back to the root of the EDA Designline Power Series.
One thing to note is that power optimization is different from the other design optimization, such as area and timing. They are absolutes and while latencies may be dependent on application usage, the maximum clock frequency that a design can operate at is dictated by the slowest path in the design. Dynamic power is application dependent. I found this great example in a paper written by Anantha P. Chandrakasan and Robert W. Brodersen from University of California at Berkeley. They say:
An important attribute which can be used in circuit and architectural optimization, is the correlation which can exist between values of a temporal sequence of data, since switching should decrease if the data is slowly changing (highly correlated). An example of the difference in the number of transitions which can be obtained for a highly correlated data stream (human speech) versus random data is shown in Figure 1 - the transition activity for a few registers in an FIR filter design. For an architecture which does not destroy the data correlation, the speech data switches 80% less capacitance than the random input. In addition, the sequencing of operations can result in large variations of the switching activity due to these temporal correlations.
Active power:
The following techniques are used to minimize active power consumption:
- Clock gating - Clock-gating provides the most amount of active power reduction for any design. Shutting off the clock for a circuit will prevent any toggle activity of the clocks or registers in a design.
- Voltage islands - Lowering the operating voltage of a design reduces the switching component of active power in a quadratic way. The signal wires in a design are typically charges to supply and discharged to ground voltage. Reducing this supply voltage decreases the overall switching power consumption. Voltage islands are specifically used for areas of a chip where performance and speed of that functional unit is non-critical but can save a lot of power.
- Dynamic Voltage and Frequency Scaling (DVFS) - Dynamic voltage and frequency scaling is by far the most complex active state power management technique. In this approach, the active operating voltage and frequency are changed based on demand of the load. During high load conditions the voltage and frequency are at nominal conditions, and the chip or unit functions to its fullest extent. During low loading conditions, the voltage or the frequency is scaled down to perform at a lower speed but provides the benefit of low active power consumption. This technique is achieved through a combined hardware and software approach.
- On-die voltage regulators - On-die voltage regulators are specifically designed to meet the demands of various active and static power requirements. In general, ICs have off-chip voltage regulator modules that can supply the voltages and current requirements for different active states. However, as the number of voltage domains increases and the need for these voltage domains to respond faster to the demand current, on-die regulators are increasingly being used in design.
- 3D-IC - Stacking ICs that communicate with one another to minimize the signal interconnect is an emerging trend in low-power design. We have seen several cases where processors and memory are stacked over a silicon interposer that makes connections using Through Silicon Vias (TSV). These interposers provide a low capacitance signal interconnect between die, thus reducing the I/O active power consumption. As the cost of 3D-ICs starts decreasing and the thermal impact is well understood, we will see a migration to 3D-IC across the industry.
Static power:
The following techniques are used to minimize static power consumption:
- Power-gating - Power-gating provides the most amount of leakage power savings for a device in standby. Simply shutting off the clocks and toggles for the functional units can only reduce the active power, whereas the unit still consumes leakage power. There are several trade-offs in power-gating that need to be understood before doing the implementation.
- Multi-vt transistor usage - One of the oldest techniques for reducing leakage power is the swapping of nominal threshold voltage (Vt) gates with higher threshold voltage (Vt) gates. In CMOS the sub-threshold leakage is inversely proportional to the threshold voltage. Higher Vt devices have a lower leakage envelope than lower Vt devices, but come at a cost of larger delays. Careful trade-off analysis needs to be done to achieve optimal leakage savings using this technique.
- Active back-bias - Active back-biasing is an approach that increases the bias voltage of the substrate nodes in CMOS gates to reduce the leakage current. This biasing technique essentially increases the threshold voltage of a unit or the entire chip during standby modes, hence decreasing the leakage power.
Shawn McCloud, VP Marketing at Calypto Design Systems adds: a 2012 survey we just completed asked this very question. 68% of respondents cited clock gating as the most common method used to reduce power followed by power gating at 35%.
References
Anantha P. Chandrakasan and Robert W. Brodersen. Minimizing Power Consumption in CMOS Circuits. http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/418/paper.fm.pdf
Other parts of this series include:
- Power 101 – Introduction
- Power 102 – Power in the flow
- Power 103 – Where is power consumed?
- Power 105 – Estimation
- Power 106 – Verification
- Power 107 – Power delivery network
- Power 108 – Futures
If you spot an error, would like to propose an improvement or addition to this entry, or anything within this power archive, please let me know by sending me an email. Your comments will be added, and your name will be preserved in the document indicating your participation in its improvement.
Go back to the root of the EDA Designline Power Series.
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Frank Eory
4/17/2012 3:57 PM EDT
This is an excellent summary of the methods most commonly used to minimize power. Great article!
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