Verification is becoming the Achilles heel of chip design in that automation of verification is not happening as fast or reliably as it is on the design side. Additionally, design relies increasingly on the incorporation of IP, and there is only a smattering of equivalent IP for verification and often misses the most complex aspects of a chip. Power adds another layer of complexity which has to be verified and requires additional tool support.Venki Venkatesh, Director of Engineering, Atrenta
says power management requires the addition of new devices to the design, such as isolation logic, power switches, level shifters and retention cells. These devices introduce new complexity to the verification problem.
But that is just one level of extra burden. Krishna Balachandran, director, low power verification marketing, Synopsys
says: power optimizations may involve sequential RTL transformations that need to be verified vs. the original RTL. The absence of such verification can lead to non-functioning SoCs or higher than desired leakage. Simulation approaches may be too slow and not cost-effective and definitely not exhaustive in nature, leading to incomplete verification coverage of power optimizations. Traditional formal equivalence tools are typically geared towards verification of combinational transformations and are inadequate for the kind of changes typically done for power optimizations. Most commercially available formal equivalence tools also suffer from capacity and performance limitations that must be overcome to handle low power designs with complex power architectural changes and hundreds of power domains. A new class of formal equivalence tools with high capacity and performance geared towards verification of sequential transformations needs to evolve in the marketplace to meet these new requirements.Lauro Rizzatti General Manager of EVE-USA
adds: power optimization presents challenges for the verification EDA vendor as well. Many low-power techniques are generally incongruent with RTL simulation or emulation, which abstracts out any notion of voltage. These digital tools must be adapted to support power intent and low-power optimization techniques that are primarily intended for implementation.
There is a further level of verification necessary and that will be covered in another in this series. I am referring to the power delivery network that creates a different class of verification problem and at the physical level, power creates problems with electromigration, noise and many other issues.
Other parts of this series include:
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Go back to the root of the EDA Designline Power Series.