Comparing four 32-bit soft processor cores

If you've been hanging around Programmable Logic Designline for any length of time, you will doubtless remember my old chum Sven-Åke Andersson from Sweden.

Sven is an ASIC designer who decided to teach himself all about FPGAs. As part of this, he decided to maintain an on-going record of the decisions he made and his progress with regard to learning and using FPGA design and verification tools and implementing his test designs. (Click Here to see my blog on Sven's Designing an FPGA from scratch tutorial.)

In fact, Sven was so successful in his endeavors that he ended up working as a consultant creating FPGA designs! On a personal note, it was great to finally meet Sven in person at the recent FPGA Forum in Norway (Click Here to see my Norwegian Odyssey [Stardate 19987+6] column).

When we met in Norway, Sven informed me that he was experimenting with a number of 32-bit soft processor cores as follows:

• The LEON3 soft processor from Aeroflex Gaisler. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture.
• The OpenRISC 1200 (OR1200). This is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture.
• The Nios II, which is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. Nios II is suitable for a wide range of embedded computing applications.
• The MicroBlaze soft processor core from Xilinx. This is a 32-bit RISC Harvard architecture soft processor core with a rich instruction set optimized for embedded applications.

The first piece of good news is that Sven has created a series of blogs about his experiences with these processors:

• Click Here to see Sven's LEON3 blogs
• Click Here to see Sven's OpenRISC blogs
• Click Here to see Sven's NIOS II blogs
• Click Here to see Sven's MicroBlaze blogs

The second piece of good news is that Sven has installed Linux and run the CoreMark benchmark on all of these processors.

And the third piece of good news is that Sven has offered to write a "How To" design article telling us about his experiences, the results from his benchmarks, and all of the interesting things he learned along the way. As soon as I have this article I will post it on Programmable Logic Designline (watch this space).

But wait, there's more, because as soon as he wraps up this project, Sven is planning to start experimenting with the new Zynq-7000 from Xilinx (the chip that combines a dual ARM Cortex-A9 hard core and programmable FPGA fabric), and he promises to share the results with me. (If you are very lucky, I might be persuaded to share these results with you [grin].) Once again... watch this space!

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