EDA/IP Weekly Roundup – May 16th

This is a roundup of news or activities in the past few days that may be of interest to people.

MathWorks has launched their DO 178 Process Deployment Advisory Service, dedicated to Model-Based Design consulting services for DO-178 projects. Aerospace engineers can gain increased confidence that high-integrity applications developed using MATLAB and Simulink comply with DO standards such as DO-178B, DO-178C, and DO-331, the Model-Based Development and Verification Supplement to DO-178C and DO-278A.

MIPS has introduced a new generation of microprocessor cores. The Aptiv Generation cores, including the proAptiv, interAptiv and microAptiv families, offer three distinct performance levels for applications across MIPS' target segments.  All based on the MIPS32® Release 3 architecture, the products are targeted towards home entertainment, networking, embedded systems segment, and mobile system development. For mobile devices, the Aptiv Generation offers multicore for applications processing in products including tablets and smartphones, multi-threading technology for applications such as baseband processing, and entry-level performance for embedded control and applications such as touchscreen controllers, SIM/security and GPS.

Imperas has released the Open Virtual Platforms (OVP) Fast Processor Models for MIPS Technologies’ new Aptiv Generation of processor cores. Example virtual platforms are also being released, as well as support for the cores in Imperas’ M*SDK advanced software development tools. MIPS Technologies has verified the functionality of the Aptiv models under the MIPS-Verified program. The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS.

Cadence announced that Netronome gained a significant performance advantage on its low-power "green" SoCs by using the Cadence® Encounter® RTL-to-GDSII flow. In addition to increased chip performance, Netronome engineers using the latest Encounter 11.1 technology achieved a 29% reduction in power consumption, smaller design area and faster overall time to market compared to their former flow, for SoCs targeting the secure virtualized cloud and data center markets. Clocks are the backbone of all digital chips, and a fundamentally different approach to clock construction and optimization was needed. Traditional clock tree synthesis (CTS) tools and methodologies -- which are based on minimizing skew and are isolated from logic/physical optimization -- are insufficient for advanced node, high-performance designs due to the growing gap between pre- and post-CTS design timing. CCOpt technology bridges the gap by re-focusing CTS directly on timing -- not skew minimization -- and combining this timing-driven CTS with concurrent logic/physical optimization.

Sigrity has introduced XcitePI IO Interconnect Model Extraction. The tool generates chip IO power/ground and signal interconnect models for system-level analysis of high-speed channels and buses. Built-in IO quality assessment capabilities enable designers to quickly check IO power/ground robustness and signal electrical performance to identify potential design defects. Dr. Jiayuan Fang, president of Sigrity, explaines that prior to Sigrity’s XcitePI IO Interconnect Model Extraction technology, simultaneous switching output (SSO) analysis was either unduly pessimistic or overly optimistic. The lack of IO interconnect models made the simulated power/ground noise at driver and receiver sides unpredictable, especially when a large number of drivers switch simultaneously.

Kilopass Technology has announced that SoC designers can select any hard IP core—IP supplied as GDSII hard macro—from the entire library of Kilopass XPM (eXtra Permanent Memory) and Gusto NVM IP, drop it into a design for fabrication at any of eight top-tier foundries at the 130/110nm node. Kilopass’ NVM IP common implementation for the eight top-tier silicon foundries at the 130/110nm process node means designers can use the same interface and achieve the same area at all of the eight foundries at 130/110nm, thus making foundry mobility simpler than before.

IC Manage has introduced its IC Manage Views™ storage acceleration software - a version aware, virtual file system that presents complete workspace views, while only transferring data on demand to a local file cache.  IC Manage Views removes network transfer bottlenecks to accelerate Electronic Design Automation (EDA) tool performance, achieve Zero-Time Sync™ (ZTS) for workspaces, and reduce storage utilization. IC Manage Views is 100% compatible with all storage technologies and works at both local and remote sites.

EVE has announced availability of a 10-Gigabit Ethernet (10GbE) validation platform for its ZeBu family of system-on-chip (SoC) hardware-assisted verification platforms.  The e-zTest 10GbE software is a transaction-based environment for high-speed validation of 10GbE functions in network routers, switches and controllers, and SoC ASICs containing 10GbE ports. EVE also announced a variety of new software to expand the capabilities of its ZeBu system-on-chip (SoC) emulation platform, including power-aware verification, post-run debugging, two vertical application validation platforms, low-power and Flash memory models, and electronic system level (ESL) tool interfaces.

Carbon Design Systems has introduced the Carbon Performance Analysis Kit (CPAK) family for accelerating the analysis, optimization and verification of system-on-chip (SoC) performance. The CPAK family for ARM Cortex A-Series processors contains reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE™ subsystem. It comes pre-configured with bare-metal initialization software, Linux or Android OS for analyzing, optimizing and verifying performance and power.  In addition, the CPAK Family is pre-configured with the multicore task migration software layer between the big.LITTLE processing cluster, which includes ARM Cortex-A15 MPCore and Cortex-A7 MPCore processors, and the client OS.

A new name has appeared in the world of analog semiconductors and sensor solutions with the announcement today by austriamicrosystems that “ams” will be its new company brand. ams, is headquartered in Unterpremstaetten. The company builds on more than 30 years of operation in analog semiconductors and has products in areas such as magnetic encoders, medical imaging, power management, low-power RF, optical sensing, audio amplification, and battery sensing. ams draws on this experience, and on the unique CMOS, High Voltage CMOS and SiGe fabrication processes it has developed, to create new high-performance standard products and ASICs targeting the consumer and communications, industrial, medical, and automotive markets all around the globe.

Brian Bailey – keeping you covered

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