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EDA/IP Weekly Roundup – May 23rd
Brian Bailey
5/23/2012 9:22 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Corelis has announced the availability of version 7.7 of its ScanExpress Boundary-Scan Tool Suite. This new version covers a wide range of new features and enhancements including improved constraints handling, support for multi-core devices, and new JTAG Embedded Test support for additional Freescale and Texas Instruments processors.
Space Codesign Systems has announced that it is a new member in the ARM Connected Community gaining them access to a full range of resources to help it market and deploy its SpaceStudio™ design tool. The SpaceStudio toolset allows embedded system designers to perform true hardware-software co-design by dragging and dropping a C function into either HW or SW implementation modules. This enables design exploration, validation and performance analysis, without the need to change application code. Design can be implemented in either an FPGA or in ASIC.
Open Core Protocol International Partnership (OCP-IP) announces the availability of an enhanced version of their Transaction Generator (TG), which is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs). The latest version now includes 8 new traffic models from Hong Kong University’s MCSL Benchmark Suite v1.1. MCSL includes two kinds of traffic patterns: recorded and statistical. Both use task communication graph model which is converted into TG’s native format automatically before simulation. These models are fine-grained having dozens or even hundreds of tasks and hence are suitable for benchmarking large systems. The default mappings utilize 16, 32 and 64 processing elements. Applications include, video processing, robot controller, and more.
Semiconductor Manufacturing International Corporation ("SMIC") has announced that SMIC is using the Calibre PERC circuit reliability verification solution from Mentor as part of its latest electrostatic discharge (ESD) protection design methodology. SMIC’s approach helps ensure whole chip ESD protection, including all I/Os, embedded IP blocks from SMIC or third-party sources, and eFuse embedded memory. Meanwhile Mentor announced that TowerJazz has selected Calibre PERC to perform circuit reliability verification for its latest 0.13 and 0.18 micron products, including electrostatic discharge (ESD) and power management circuit checks. And to round things out Mentor also announced that GLOBALFOUNDRIES is adding Calibre PERC to select 28nm bulk CMOS design enablement flows. Calibre PERC will give designers access to the new reliability verification rules developed by the IBM Semiconductor Development Alliance (ISDA), augmented with GLOBALFOUNDRIES specific checks to help prevent external latch-up.
NanGate has announced the release of its V5 Library Creator Platform for advanced process node SoC design, including support for 20/22nm process technology. This release adds new cell compaction and cell routing technology that reduces manual effort for new cell creation and process migration, resulting in faster turn-around times and productivity gains.
Tanner EDA and Aldec have collaborated on an integrated co-simulation solution for analog and mixed-signal (A/MS) design. Tanner EDA’s new HiPer Simulation A/MS offers their T-Spice analog design capture and simulation tool together with Aldec’s Riviera-PRO™ mixed language digital simulator. The solution allows both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. Creating and verifying A/MS integrated circuits is a challenge. Spice-based simulation provides the accuracy needed for the analog design, but is too slow to handle the digital part. Event-driven digital simulation provides the necessary speed to simulate the digital portions, but fails when dealing with the analog parts.
Imperas has announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with NEC’s CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP’s instruction accurate processor core models expand CyberWorkBench’s C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Corelis has announced the availability of version 7.7 of its ScanExpress Boundary-Scan Tool Suite. This new version covers a wide range of new features and enhancements including improved constraints handling, support for multi-core devices, and new JTAG Embedded Test support for additional Freescale and Texas Instruments processors.
Space Codesign Systems has announced that it is a new member in the ARM Connected Community gaining them access to a full range of resources to help it market and deploy its SpaceStudio™ design tool. The SpaceStudio toolset allows embedded system designers to perform true hardware-software co-design by dragging and dropping a C function into either HW or SW implementation modules. This enables design exploration, validation and performance analysis, without the need to change application code. Design can be implemented in either an FPGA or in ASIC.
Open Core Protocol International Partnership (OCP-IP) announces the availability of an enhanced version of their Transaction Generator (TG), which is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs). The latest version now includes 8 new traffic models from Hong Kong University’s MCSL Benchmark Suite v1.1. MCSL includes two kinds of traffic patterns: recorded and statistical. Both use task communication graph model which is converted into TG’s native format automatically before simulation. These models are fine-grained having dozens or even hundreds of tasks and hence are suitable for benchmarking large systems. The default mappings utilize 16, 32 and 64 processing elements. Applications include, video processing, robot controller, and more.
Semiconductor Manufacturing International Corporation ("SMIC") has announced that SMIC is using the Calibre PERC circuit reliability verification solution from Mentor as part of its latest electrostatic discharge (ESD) protection design methodology. SMIC’s approach helps ensure whole chip ESD protection, including all I/Os, embedded IP blocks from SMIC or third-party sources, and eFuse embedded memory. Meanwhile Mentor announced that TowerJazz has selected Calibre PERC to perform circuit reliability verification for its latest 0.13 and 0.18 micron products, including electrostatic discharge (ESD) and power management circuit checks. And to round things out Mentor also announced that GLOBALFOUNDRIES is adding Calibre PERC to select 28nm bulk CMOS design enablement flows. Calibre PERC will give designers access to the new reliability verification rules developed by the IBM Semiconductor Development Alliance (ISDA), augmented with GLOBALFOUNDRIES specific checks to help prevent external latch-up.
NanGate has announced the release of its V5 Library Creator Platform for advanced process node SoC design, including support for 20/22nm process technology. This release adds new cell compaction and cell routing technology that reduces manual effort for new cell creation and process migration, resulting in faster turn-around times and productivity gains.
Tanner EDA and Aldec have collaborated on an integrated co-simulation solution for analog and mixed-signal (A/MS) design. Tanner EDA’s new HiPer Simulation A/MS offers their T-Spice analog design capture and simulation tool together with Aldec’s Riviera-PRO™ mixed language digital simulator. The solution allows both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. Creating and verifying A/MS integrated circuits is a challenge. Spice-based simulation provides the accuracy needed for the analog design, but is too slow to handle the digital part. Event-driven digital simulation provides the necessary speed to simulate the digital portions, but fails when dealing with the analog parts.
Imperas has announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with NEC’s CyberWorkBench (CWB) SystemC cycle-accurate hardware models. OVP’s instruction accurate processor core models expand CyberWorkBench’s C/SystemC SoC design flow including ANSI-C/SystemC synthesis, hardware-software (HW/SW) co-verification and C-based formal.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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