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Synopsys announces hybrid prototyping
Brian Bailey
6/4/2012 10:23 AM EDT
This is a product announcement that I have been expecting for over two years now. It was hinted at in the FAQ of a previous product when Synopsys first started getting into the virtual prototyping space and then acquired their FPGA prototyping technology. It was only a matter of time before they brought the two pieces together into a hybrid prototype capable of using both high level models running in Virtualizer and legacy IP, or fully implemented blocks running on a physical prototype, such as HAPS.
The system works by using the logical boundary that exists within most SoC, namely the busses. Transactor models exist for these entities that enable the step in abstraction that exist at these boundaries and using the Synopsys UMRbus transport mechanism, a seamless interface can be made between the environments. It is also possible to use industry standard APIs such as Accellera SCE-MI. Multiple busses are supported with multiple modes of synchronization possible, ranging from lockstep to free running enabling a tradeoff between accuracy and execution performance.
But it is also clear that this is the first stage in the product release. When parts of the design are migrated between the environments, some levels of cross triggering are possible. For the HW guys, normal types of debug will still be possible as well using the Synplify tools suite. At this point in time it is not possible to monitor the hardware in the virtual world when it has been mapped into the FPGA meaning that there will be limited hardware/software co-debug.
In the past, the two types of prototypes have been in the domain of different specialists separated by the natural timeline of the project. Both types of prototype offer near real time performance individually, but designers lacked the ability to bring the two together in a natural manner, without having to perform a lot of manual effort.
The use of the physical prototyping also allows connection to real world I/O which can help with the creation of realistic data flows. While the Virtual prototype has been able to use I/O in the past, it did not utilize the actual IP. With the physical connection, that part of the system can be fully verified as well providing greater flexibility in the type of verification environment created.
This is in the hands of early adopters now.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
The system works by using the logical boundary that exists within most SoC, namely the busses. Transactor models exist for these entities that enable the step in abstraction that exist at these boundaries and using the Synopsys UMRbus transport mechanism, a seamless interface can be made between the environments. It is also possible to use industry standard APIs such as Accellera SCE-MI. Multiple busses are supported with multiple modes of synchronization possible, ranging from lockstep to free running enabling a tradeoff between accuracy and execution performance.
But it is also clear that this is the first stage in the product release. When parts of the design are migrated between the environments, some levels of cross triggering are possible. For the HW guys, normal types of debug will still be possible as well using the Synplify tools suite. At this point in time it is not possible to monitor the hardware in the virtual world when it has been mapped into the FPGA meaning that there will be limited hardware/software co-debug.
In the past, the two types of prototypes have been in the domain of different specialists separated by the natural timeline of the project. Both types of prototype offer near real time performance individually, but designers lacked the ability to bring the two together in a natural manner, without having to perform a lot of manual effort.
The use of the physical prototyping also allows connection to real world I/O which can help with the creation of realistic data flows. While the Virtual prototype has been able to use I/O in the past, it did not utilize the actual IP. With the physical connection, that part of the system can be fully verified as well providing greater flexibility in the type of verification environment created.
This is in the hands of early adopters now.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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