EDA DesignLine Blog
Tell us What You Think
We want to know what you thought about this Discussion. Let us know by adding a comment.
EDA/IP Weekly Roundup – June 6th
Brian Bailey
6/6/2012 10:32 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Cadence says that it has contributed to STMicroelectronics having taped out a 20-nanometer test chip, incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node. Engineers from the two companies collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff, in addition to development of foundational IP and a SKILL-based process design kit (PDK) for the 20-nanometer process.
Synopsys says that TSMC has given Phase I Certification to Synopsys design implementation tools for its 20-nm process. TSMC certified the tools for its 20-nm design rule manuals (DRMs) and SPICE models. Certified products include Synopsys' IC Compiler™ for physical design; IC Validator for DRC and LVS; StarRC™ for extraction; and Galaxy Custom Designer® for custom implementation. Certification of PrimeTime® for static timing analysis is in progress. Certification covers all the relevant 20-nm technology files including routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kit (iPDK).
Similarly, ATopTech has received TSMC Phase I Certification for its Aprisa™ place and route technology. TSMC certified Aprisa for 20nm design rule manuals (DRMs) and SPICE models.
Not to be outdone, Cadence said that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals (DRMs) and SPICE models. In addition Cadence® Physical Verification System (PVS) was qualified for 28-nanometer design signoff, and completed Phase I certification for TSMC's 20-nanometer process.
GLOBALFOUNDRIES is demonstrating an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG). The flow provides support for advanced analog/mixed-signal (AMS) design using the industry’s latest design automation technology. In addition, the company will reveal jointly developed design flows with its EDA partners in certifying both analog and digital “double patterning aware” flows for its 20nm process, with silicon validation expected in early 2013 at that technology node.
OneSpin Solutions has secured new funding from its major shareholder, Azini Capital. The investment will finance strategic extensions to the company’s portfolio of solutions for the formal verification and equivalence checking of both SoC/ASIC and FPGA designs, together with the development and deployment of a range of solutions targeted at new adopters. The company also has announced a management change, with Raik Brinkmann, who joined the company at its inception in 2005, assuming the role of President and Chief Executive Officer, to lead and manage the company’s growth strategy.
MunEDA and Agilent Technologies Inc. have integrated MunEDA’s software product WiCkeD for circuit porting, analysis and optimization with Agilent’s GoldenGate RFIC simulation and analysis software to enhance and speed up the analysis, modeling and optimization of RF circuits. The integrated solution is now available for customer use. MunEDA’s WiCkeD is a software tool suite for the sizing (including porting), analysis, modeling, optimization, and verification of analog/mixed-signal and full-custom digital circuit designs and IP libraries. Agilent GoldenGate RFIC simulation and analysis software is for integrated RF circuit design.
S2C has added ARM1176 and ARM926 Global Unichip Corp (GUC) test chip modules to their family of Prototype Ready accessories used to create FPGA-based prototypes and to interface FPGA-based prototype boards to the user's target operating environment. The 2 new ARM test chip modules can be used with all S2C SoC/ASIC prototyping hardware including Virtex-7 TAI Logic Modules, Stratix-4 TAI Logic Modules, Stratix-4 TAI Verification modules, Virtex-6 TAI Logic Modules and Virtex-6 TAI Verification Modules.
Target Compiler Technologies has announced that Huawei and Dialog Semiconductor have adopted Target’s IP Designer™ tool-suite. Huawei is using IP Designer to design DSP cores for next generation wireless communication devices. By using IP Designer, Huawei plans to increase real-time performance, power efficiency, and flexibility of future baseband SoCs. Dialog Semiconductor is using it to create a new embedded graphics processor core. It enabled the design of the processor architecture and hardware, and the implementation of the OpenVG™ 1.1 embedded graphics API, for integration into Dialog Semiconductor’s recently announced Green VoIP™ “SC14453” multicore system-on-chip (SoC).
Atrenta has announced the availability of a fast lint methodology for its SpyGlass RTL analysis and optimization platform. The new capability is part of Atrenta’s GuideWare reference methodology, and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results. The SpyGlass linting solution analyzes a design at the register transfer level (RTL) of abstraction for coding styles and circuit constructs that can cause verification and implementation issues. Linting forms the base capability for the SpyGlass platform, which is also used widely for power optimization, clock synchronization verification (CDC), testability, constraints management and routing congestion analysis.
Sagantec says that Vanguard International Semiconductor Corporation (VIS) has adopted Sagantec's process migration solution for its standard cell libraries to be able to quickly migrate its IP or modify it to accommodate customer needs. Using the Sagantec solution, VIS library development will be able to meet customer’s tight prototyping schedule. VIS has already successfully migrated a library from one process to another process using the Sagantec solution.
Synopsys and Cadence have independently announced the results of collaboration with Samsung Electronics for their 20-nanometer (nm) process geometry. These include double patterning capabilities. Double patterning is a key new approach to lithography that enables higher routing density for advanced process nodes. Double patterning splits each metal layer of designs into two masks for chip fabrication, enabling higher metal density and smaller silicon area for process technologies at 20-nanometers and below.
GLOBALFOUNDRIES has announced support for Agilent's GoldenGate RFIC circuit and Momentum 3D planar electromagnetic (EM) simulators for its 65nm Low Power enhanced (LPe). Process and model compatibility between baseband and RF processes ensures intellectual property designed for baseband products is fully transferrable to the RF CMOS SoC solution. With its suite of RF components, low leakage transistors, VNCAP (metal-oxide-metal capacitor), MIM (metal-insulator-metal capacitor), thick metal inductors, and varactors, the 65nm - LPe RF CMOS process provides an ideal platform for low power and high-performance SoC solutions.
Mentor is not to be left out of the EDA/foundry flurry of announcements. They have announced that the Calibre physical verification platform is now available for TSMC’s 20nm manufacturing process. TSMC has given Phase I Certification to Mentor’s Calibre, certifying it for TSMC design rule manuals (DRMs) and SPICE models. Current certifications address elements of the Calibre platform including innovative patterning, DRC, LVS and extraction. They also announced that TSMC will use Calibre pattern matching (PM) capabilities within its Unified DFM Engine for 20nm litho process checking (LPC). The Calibre PM facility provides pattern-based analysis to identify potential litho yield detractors (high-risk features known to be difficult to image) that may be present in the layout.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Cadence says that it has contributed to STMicroelectronics having taped out a 20-nanometer test chip, incorporating custom analog and digital methodologies to enable mixed-signal SoC design at this advanced process node. Engineers from the two companies collaborated closely to develop technologies and deploy methodologies using the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff, in addition to development of foundational IP and a SKILL-based process design kit (PDK) for the 20-nanometer process.
Synopsys says that TSMC has given Phase I Certification to Synopsys design implementation tools for its 20-nm process. TSMC certified the tools for its 20-nm design rule manuals (DRMs) and SPICE models. Certified products include Synopsys' IC Compiler™ for physical design; IC Validator for DRC and LVS; StarRC™ for extraction; and Galaxy Custom Designer® for custom implementation. Certification of PrimeTime® for static timing analysis is in progress. Certification covers all the relevant 20-nm technology files including routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kit (iPDK).
Similarly, ATopTech has received TSMC Phase I Certification for its Aprisa™ place and route technology. TSMC certified Aprisa for 20nm design rule manuals (DRMs) and SPICE models.
Not to be outdone, Cadence said that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals (DRMs) and SPICE models. In addition Cadence® Physical Verification System (PVS) was qualified for 28-nanometer design signoff, and completed Phase I certification for TSMC's 20-nanometer process.
GLOBALFOUNDRIES is demonstrating an enhanced silicon-validated design flow for its 28nm Super Low Power (SLP) technology with Gate First High-k Metal Gate (HKMG). The flow provides support for advanced analog/mixed-signal (AMS) design using the industry’s latest design automation technology. In addition, the company will reveal jointly developed design flows with its EDA partners in certifying both analog and digital “double patterning aware” flows for its 20nm process, with silicon validation expected in early 2013 at that technology node.
OneSpin Solutions has secured new funding from its major shareholder, Azini Capital. The investment will finance strategic extensions to the company’s portfolio of solutions for the formal verification and equivalence checking of both SoC/ASIC and FPGA designs, together with the development and deployment of a range of solutions targeted at new adopters. The company also has announced a management change, with Raik Brinkmann, who joined the company at its inception in 2005, assuming the role of President and Chief Executive Officer, to lead and manage the company’s growth strategy.
MunEDA and Agilent Technologies Inc. have integrated MunEDA’s software product WiCkeD for circuit porting, analysis and optimization with Agilent’s GoldenGate RFIC simulation and analysis software to enhance and speed up the analysis, modeling and optimization of RF circuits. The integrated solution is now available for customer use. MunEDA’s WiCkeD is a software tool suite for the sizing (including porting), analysis, modeling, optimization, and verification of analog/mixed-signal and full-custom digital circuit designs and IP libraries. Agilent GoldenGate RFIC simulation and analysis software is for integrated RF circuit design.
S2C has added ARM1176 and ARM926 Global Unichip Corp (GUC) test chip modules to their family of Prototype Ready accessories used to create FPGA-based prototypes and to interface FPGA-based prototype boards to the user's target operating environment. The 2 new ARM test chip modules can be used with all S2C SoC/ASIC prototyping hardware including Virtex-7 TAI Logic Modules, Stratix-4 TAI Logic Modules, Stratix-4 TAI Verification modules, Virtex-6 TAI Logic Modules and Virtex-6 TAI Verification Modules.
Target Compiler Technologies has announced that Huawei and Dialog Semiconductor have adopted Target’s IP Designer™ tool-suite. Huawei is using IP Designer to design DSP cores for next generation wireless communication devices. By using IP Designer, Huawei plans to increase real-time performance, power efficiency, and flexibility of future baseband SoCs. Dialog Semiconductor is using it to create a new embedded graphics processor core. It enabled the design of the processor architecture and hardware, and the implementation of the OpenVG™ 1.1 embedded graphics API, for integration into Dialog Semiconductor’s recently announced Green VoIP™ “SC14453” multicore system-on-chip (SoC).
Atrenta has announced the availability of a fast lint methodology for its SpyGlass RTL analysis and optimization platform. The new capability is part of Atrenta’s GuideWare reference methodology, and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results. The SpyGlass linting solution analyzes a design at the register transfer level (RTL) of abstraction for coding styles and circuit constructs that can cause verification and implementation issues. Linting forms the base capability for the SpyGlass platform, which is also used widely for power optimization, clock synchronization verification (CDC), testability, constraints management and routing congestion analysis.
Sagantec says that Vanguard International Semiconductor Corporation (VIS) has adopted Sagantec's process migration solution for its standard cell libraries to be able to quickly migrate its IP or modify it to accommodate customer needs. Using the Sagantec solution, VIS library development will be able to meet customer’s tight prototyping schedule. VIS has already successfully migrated a library from one process to another process using the Sagantec solution.
Synopsys and Cadence have independently announced the results of collaboration with Samsung Electronics for their 20-nanometer (nm) process geometry. These include double patterning capabilities. Double patterning is a key new approach to lithography that enables higher routing density for advanced process nodes. Double patterning splits each metal layer of designs into two masks for chip fabrication, enabling higher metal density and smaller silicon area for process technologies at 20-nanometers and below.
GLOBALFOUNDRIES has announced support for Agilent's GoldenGate RFIC circuit and Momentum 3D planar electromagnetic (EM) simulators for its 65nm Low Power enhanced (LPe). Process and model compatibility between baseband and RF processes ensures intellectual property designed for baseband products is fully transferrable to the RF CMOS SoC solution. With its suite of RF components, low leakage transistors, VNCAP (metal-oxide-metal capacitor), MIM (metal-insulator-metal capacitor), thick metal inductors, and varactors, the 65nm - LPe RF CMOS process provides an ideal platform for low power and high-performance SoC solutions.
Mentor is not to be left out of the EDA/foundry flurry of announcements. They have announced that the Calibre physical verification platform is now available for TSMC’s 20nm manufacturing process. TSMC has given Phase I Certification to Mentor’s Calibre, certifying it for TSMC design rule manuals (DRMs) and SPICE models. Current certifications address elements of the Calibre platform including innovative patterning, DRC, LVS and extraction. They also announced that TSMC will use Calibre pattern matching (PM) capabilities within its Unified DFM Engine for 20nm litho process checking (LPC). The Calibre PM facility provides pattern-based analysis to identify potential litho yield detractors (high-risk features known to be difficult to image) that may be present in the layout.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
|
|
|
|
|
Navigate to related information