This is a roundup of news or activities in the past few days that may be of interest to people.
Mentor Graphics has added hibernate mode to its Mentor Embedded Nucleus real time operating system (RTOS) Power Management Framework. Using the Nucleus RTOS, embedded software developers can minimize power consumption by taking advantage of the latest power saving technology, including dynamic voltage and frequency scaling (DVFS), clock gating and standby, and hibernate states—common in today’s processors. The first in a line of industry-leading devices to be supported with hibernate capability of the Nucleus Power Management Framework is the Freescale i.MX family of multimedia processors.
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) have announced availability of version 5.0 of their 40-nanometer (nm) RTL-to-GDSII reference design flow. This production-proven flow incorporates a broad range of automated low power and high-performance capabilities. The reference flow is the result of collaboration between SMIC and Synopsys Professional Services. The reference flow features new high-performance design techniques, including automated clock mesh synthesis, plus a gate array engineering change order (ECO) flow that allows a designer to quickly achieve design closure without having to start from scratch with a redesign. The reference flow also includes support for low power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low power design intent standard.
Synopsys has announced that Infineon Technologies has used Synopsys' Virtualizer tool set to deploy virtual prototypes of their AURIX microcontroller-based systems, enabling early software development and customer engagement prior to silicon availability. The AURIX virtual prototype, a fast, functional model of the AURIX multicore microcontrollers, is now an integral part of the suite of development tools provided by Infineon to accelerate its customers' development and deployment of real-time embedded software.
Cadence Design Systems says that Ambarella, a maker of high-definition video compression and image-processing solutions for consumer cameras and television broadcasting, realized gains on a recent 32-nanometer gigahertz SoC design by upgrading to the latest Cadence Encounter RTL-to-GDSII flow. Using the latest Encounter technology, version 11.1, Ambarella saw a 15 percent improvement in performance and a 6.4 percent reduction in power consumption over the prior Cadence technology when designing the encoder/transcoder SoC.
Analog Devices has announced a new release of the NI Multisim Component Evaluator – Analog Devices Edition. In collaboration with National Instruments, the new version of the free tool adds features and functionality to provide engineers with an easy-to-use environment for the simulation of linear circuits using ADI components. The new release of the Multisim – ADI Edition includes more than 870 models of ADI’s linear components. By pairing these components with simulation features and SPICE analyses, engineers can now visualize and evaluate linear performance. The free component evaluation tool is available for download on ADI’s website at http://www.analog.com/multisim.
Xilinx is providing a solution for designs using the Virtex-7 FPGA integrated block for PCI Express x8 Gen3 with DDR3 external memory, providing developers with the building blocks needed to get started on PCI Express Gen3-based designs. The Xilinx integrated blocks for the PCI Express Gen3 standard along with support for 1866 Mb/s high speed memory interfaces in mid-speed grade devices allow users to design systems that meet system bandwidth requirements needed in communications, storage, server applications, and more.Brian Bailey
– keeping you covered
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