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EDA/IP Weekly Roundup – July 11th
Brian Bailey
7/11/2012 9:57 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Mentor Graphics has announced the Nucleus product integration and SMP (symmetric multiprocessing) support for the MIPS32 34K core that utilizes MIPS Technologies' MT (hardware Multi-Threading) technology. The combination demonstrated increased embedded application performance of over 20%, without increasing power consumption or silicon size. Mentor claims that the Nucleus product is the industry's first RTOS to demonstrate significant performance gains using MIPS Technologies' Virtual Processing Engines (VPEs) over a single-core approach.
Synopsys has announced that its PCI Express controller IP with support for low-power sub-states has successfully taped out in multiple designs. The addition of the L1.1 ("snooze") and L1.2 ("off") sub-states to Synopsys' DesignWare® controller IP for PCI Express 1.0, 2.0 and 3.0 enables designers to reduce power consumption in key market segments, including camera, card reader, networking and wireless applications serving the ultrabook and tablet markets. L1 sub-states reduce a PCI Express system's link idle power consumption from 15 to 20 milliwatts per lane to 10microwatts per lane, or by approximately 99 percent, by repurposing the signals between the PHY and the controller so that they turn off the high-speed circuits in the PHY when not in use.
Synopsys and Semiconductor Manufacturing International Corporation are making availability a set of Synopsys DesignWare IP on the SMIC 40-nanometer (nm) low-leakage (40LL) process. The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric. Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:
Altera has announced the production availability of its 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba™-2010 standard compliant, reducing design complexity for customers integrating 40GbE and 100GbE connections on Altera’s 28-nm Stratix® V FPGAs and 40-nm Stratix IV FPGAs.
Aldec with Agilent Technologies have created a new co-simulation interface between Riviera-PRO, a design simulation and verification platform and SystemVue, an ESL design and signal processing environment. The new solution enables users to efficiently integrate algorithm and system-level designs with hardware implementations.
Cadence has updated its PCI Express Verification IP which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. Support for the new PCIe PIPE4 specification includes; new performance measurement features critical for optimizing PCIe implementation; TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance; and Accelerated PCIe VIP that drives the verification speed required for large SoCs. This release addresses the full spectrum of PCIe applications and supports the latest specifications, including SR-IOV, MR-IOV, NVMe and PIPE4.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Mentor Graphics has announced the Nucleus product integration and SMP (symmetric multiprocessing) support for the MIPS32 34K core that utilizes MIPS Technologies' MT (hardware Multi-Threading) technology. The combination demonstrated increased embedded application performance of over 20%, without increasing power consumption or silicon size. Mentor claims that the Nucleus product is the industry's first RTOS to demonstrate significant performance gains using MIPS Technologies' Virtual Processing Engines (VPEs) over a single-core approach.
Synopsys has announced that its PCI Express controller IP with support for low-power sub-states has successfully taped out in multiple designs. The addition of the L1.1 ("snooze") and L1.2 ("off") sub-states to Synopsys' DesignWare® controller IP for PCI Express 1.0, 2.0 and 3.0 enables designers to reduce power consumption in key market segments, including camera, card reader, networking and wireless applications serving the ultrabook and tablet markets. L1 sub-states reduce a PCI Express system's link idle power consumption from 15 to 20 milliwatts per lane to 10microwatts per lane, or by approximately 99 percent, by repurposing the signals between the PHY and the controller so that they turn off the high-speed circuits in the PHY when not in use.
Synopsys and Semiconductor Manufacturing International Corporation are making availability a set of Synopsys DesignWare IP on the SMIC 40-nanometer (nm) low-leakage (40LL) process. The SMIC 40LL process technology combines advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric. Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:
- Interface IP for widely used protocols such as USB 2.0/3.0, PCI Express 2.0/1.1, MIPI, SATA, DDR, and HDMI that reduces interoperability risk
- Audio codec and data converter IP, optimized for a wide range of high-performance, low-power applications
- Embedded memories and logic libraries that enable designers to achieve both high speed and low power across the entire SoC
Altera has announced the production availability of its 40-Gbps Ethernet (40GbE) and 100-Gbps Ethernet (100GbE) intellectual property (IP) cores. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba™-2010 standard compliant, reducing design complexity for customers integrating 40GbE and 100GbE connections on Altera’s 28-nm Stratix® V FPGAs and 40-nm Stratix IV FPGAs.
Aldec with Agilent Technologies have created a new co-simulation interface between Riviera-PRO, a design simulation and verification platform and SystemVue, an ESL design and signal processing environment. The new solution enables users to efficiently integrate algorithm and system-level designs with hardware implementations.
Cadence has updated its PCI Express Verification IP which result in more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. Support for the new PCIe PIPE4 specification includes; new performance measurement features critical for optimizing PCIe implementation; TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance; and Accelerated PCIe VIP that drives the verification speed required for large SoCs. This release addresses the full spectrum of PCIe applications and supports the latest specifications, including SR-IOV, MR-IOV, NVMe and PIPE4.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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