EDA/IP Weekly Roundup – July 25th

7/25/2012 9:37 AM EDT

This is a roundup of news or activities in the past few days that may be of interest to people.

Mentor Graphics has invested $825,000 in Portland State University’s Maseeh College of Engineering and Computer Science to advance the study of integrated circuit design in the new Mentor Graphics Design Verification and Emulation Lab. In 2009, the company gave PSU an emulator worth approximately $1 million. This new investment includes a $700,000 gift over five years for a new faculty member, to be hired by June 2013, and $125,000 for options for exclusive access to intellectual property based on research conducted in the lab. Two PSU professors are already working in the emulation field, and PSU plans to hire an additional faculty member using PSU funds for a total of four faculty members in the lab.

Aldec  and Test and Verification Solutions (TVS) have partnered to deliver new Verification IP (VIP) via Aldec’s Unite IP Partner ecosystem. TVS offers asureVIP, a highly flexible and configurable UVM/OVM or eRM compliant VIP portfolio, now validated with Riviera-PRO.  Aldec’s customer base can now access a off-the-shelf VIP components (SPI, I2C, SDCARD, UART, AHB, AXI-4, USB, and others) from TVS which can be integrated into their SOC verification platform.

TSMC and ARM have announced a multi-year agreement extending their collaboration beyond 20-nanometer (nm) technology to deliver ARM processors on FinFET transistors, enabling the fabless industry to extend its market leadership in application processors. The collaboration will optimize the next generation of 64-bit ARM® processors based on the ARMv8 architecture, ARM Artisan® physical intellectual property (IP), and TSMC’s FinFET process technology for use in mobile and enterprise markets that require both high performance and energy efficiency.

S2C, the organizer of the SoCIP show, announced that the SoCIP 2012 show held in Shanghai and Beijing was a success, with over 300 qualified attendees.  The conference addressed many new design and verification challenges arising from building the next generation SoC such as for mobile computing, consumer electronics and communication systems.  A series of seminar sessions were presented throughout the day by SpringSoft, Tensilica, Algotochip, CAST, Cosmic, Mindtree, IP Goal and S2C.  Conference attendee also had opportunities to discuss challenges and solutions face-to-face with experts from the participating EDA and IP suppliers.

Esterel Technologies has announced the SCADE LifeCycle Qualified Test Environment (QTE) and its interface with the LDRA tool suite. SCADE LifeCycle QTE is a module that allows developers of certifiable applications to automate running test cases created during model-based verification activities on host and on target, thus allowing a complete verification workflow from high-level requirements-based testing on model down to integration testing on target.  SCADE Lifecycle QTE for LDRA integrates model-based application development with SCADE Suite and the LDRA tool suite. On-target testing is required to achieve the most rigorous levels of DO-178C compliance. Model-based applications can now be automatically passed to TBrun, the unit testing component in the LDRA tool suite, which ensures that the embedded application is running as expected on the target.

Synopsys and TowerJazz have jointly qualified Synopsys' unified mixed-signal IC design solution for TowerJazz's power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys' tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.

Synopsys has updated the Virtualizer tool set for creating virtual prototypes and Virtualizer Development Kits (VDKs). The new Virtualizer release improves modeling productivity through its new model authoring feature and IP specification import function, enabling engineers to develop system-level models and assemble them into virtual prototypes up to three times faster. In addition, enhanced support for popular debugger tools allows software developers to easily integrate Virtualizer-based virtual prototypes into their existing software debug flows.