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EDA/IP Weekly Roundup – August 15th
Brian Bailey
8/15/2012 7:26 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
ARM and Cadence have announced the availability of the first in a series of combined solutions enabling designers to improve performance, power and time-to-market for ARM® Cortex™-A series processor-based system-on-chips (SoCs). The initial solution optimizes ARM® POP™ intellectual property (IP) technology, using the Cadence® Encounter® digital platform, for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The resulting solution is available for license from ARM to accelerate the implementation of ARM processors.
GLOBALFOUNDRIES and ARM have announced a multi-year agreement to jointly deliver optimized system-on-chip (SoC) solutions for ARM® processor designs on GLOBALFOUNDRIES’ 20-nanometer (nm) and FinFET process technologies. The agreement also extends the collaboration to include graphics processors. As part of the agreement, ARM will develop a full platform of ARM Artisan® Physical IP, including standard cell libraries, memory compilers and POP™ IP solutions.
Cadence has announced availability of the comprehensive design methodology book for chip designers and CAD engineers that focuses on current and future advanced mixed-signal design challenges and solutions. The "Mixed-Signal Methodology Guide" provides an overview of the design, verification and implementation methodologies required for advanced mixed-signal designs. The book brings together top mixed-signal design experts from across the industry -- including authors from Boeing, Cadence®, ClioSoft and Qualcomm -- to address the complex problems facing the mixed-signal design community.
Verific Design Automation has licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec to be included into its Hardware Emulation Solution (HES). HES is a unified platform for bit-level simulation acceleration, transaction-level emulation, system architecture exploration, hardware/software co-verification, virtual modeling and prototyping. Verific’s SystemVerilog and VHDL parsers and register transfer level (RTL) elaborators have been integrated with its Design Verification Manager (DVM) software.Brian Bailey – keeping you covered
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