Book excerpt: High-level synthesis blue book

9/4/2012 1:09 PM EDT

High-level synthesis blue book - Michael Fingeroff - Calypto

The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification. In other words, HLS automates an otherwise manual process, eliminating the source of many design errors and accelerating a very long and iterative part of the development cycle.

I talked to Michael about the book. First, I asked him why he had written the book.

Michael: After spending years being involved in high-level synthesis, there is a lot of uncertainty about how to go about writing C code for synthesis. There are no books out there that tell you how to go about writing un-timed C code in order to get good quality hardware. For years there was a misconception that you could just take C code, throw it into the tool and get out hardware based on a set of constraints. This is hardware design and the language just happens to be C rather than Verilog. I have always liked cook books that give me the recipe for how to do something, then I can take that and run with it. When you start to deal with algorithms that have arrays that need to be mapped to memories, the array access pattern of the algorithm dictates the underlying performance of the hardware that you are going to be able to realize. Understanding how to analyze and restructure your algorithm is where you spend a lot of time.

The book first came out two years ago. Is it still current?

It is just as valid today except that it doesn’t cover SystemC. However, most of it is still valid because in SystemC allows you to mix different levels of abstraction, plus it has explicit concurrency. While SystemC allows you define specific threads, within those threads, you are still doing untimed C design. So all of the design techniques still apply.

How much adoption is there of high-level synthesis?

We are seeing a much larger interest recently. While there is still a certain amount of skepticism, we are normally able to prove them wrong. Some think this tool is supposed to replace them, but then they see that it can make them more productive and leverages the kind of knowledge they have about architectures, memories and other hardware decisions. Others are skeptical about the ability to take an untimed language and build hardware out of that.

Many customers report that they get bigger productivity gains in verification than design from using high-level synthesis. What plans do you have to integrate this technology into the Calypto SLEC technology?

You are right, and integrating high-level synthesis with formal verification is the holy grail of high-level synthesis. It enables you to verify problems that you can’t possibly exercise using traditional verification methods. Trying to simulate sufficient numbers of lengths of tests at RTL is just not possible. That was one of the overriding reasons why we brought these technologies together into a single company.

I will be excerpting from two chapter of the book. In this first group I will be presenting pieces of chapter 6 on the subject of Sequential and combinational hardware. Three examples types of circuits will be shown that represent most of the concepts that you would need to know. Then, I will excerpt from chapter 5 which talks about Scheduling of I/O and memories. This is a subject I often get questions about, so I wanted you to see the way in which Catapult handles this today.

Will there be another book?

Yes, that is my plan. Not only is there more to go into untimed content, but also more related to SystemC.

Thanks Mike!

To get a copy of this book click here

Chapter listing

Making the case for high-level synthesis

General C++ Style

Bit accurate data types

Fundamentals of high-level synthesis

Scheduling of I/O and memories – will be excerpted

Sequential and combinational hardware – will be excerpted

Memory Architecture

Hierarchical design

Advanced hierarchical design

Digital filters

FFT transform

Chapter 6 Sequential and combinational hardware

Introduction

The previous chapters provided a good introduction to the principles behind high-level synthesis and the use of bit-accurate data types. The basics of scheduling and loop optimizations were illustrated using concepts familiar to RTL designers, such as hardware diagrams, state machines, and timing diagrams. The next logical step is to take this foundation and apply it to some real world hardware examples. In a similar fashion to most RTL design guides, this chapter presents many of the basic hardware structures that RTL designers are familiar with, and shows how to code them using synthesizable C++. Unlike the examples of previous chapters, which focused primarily on a C-like coding style, class-based/object oriented C++ is introduced, including templates and recursion. As this chapter progresses the reader can begin to see the true power of hardware design using C++. The hardware examples presented in this chapter are all depicted as sequential circuits. This is because it is assumed that each example is synthesized as the top-level design. When used in the context of a larger design these circuits may be sequential or combinational based on the clock frequency and how the design is scheduled. True combinational components can also be synthesized by using explicit directives in the C++ synthesis tool.

Chapter contents (highlighted subjects will be provided in excerpts)

Shift Registers – provided in this excerpt

Helper Classes for Design Reuse

Multiplexors

Priority Search Hardware – next week

Shifters

Adder Trees – future

Lookup Tables (LUT)

To get a copy of this book click here

Chapter 5 Scheduling of I/O and memories

Similar to loop pipelining and loop unrolling, the way in which IO and memory accesses are coded in a design can have a significant impact on both area and performance. IO and memory accesses tend to be the bottleneck in a system and they can potentially limit the ability to pipeline a design, or negate the benefits gained from loop unrolling. In the worst case using bad style when coding IO or memories prevents scheduling a design.

There are two primary ways for passing IO into and out of a design, pass by value and pass by pointer or reference, which includes arrays. Using one over the other can lead to very different behavior.

Chapter contents (highlighted subject will be provided)

Unconditional IO

Conditional IO

Memories

To get a copy of this book click here

Other book excerpts:

Power Integrity Modeling and Design for Semiconductors and Systems

Introduction to Open Core Protocol