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EDA/IP Weekly Roundup – September 5th
Brian Bailey
9/5/2012 10:52 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Sonics has joined the HSA (Heterogeneous System Architecture) Foundation as a contributor member, collaborating with other major industry leaders to support the parallel computing efforts for next-generation heterogeneous processors. In June at the AMD Fusion Developer Summit, major global technology leaders converged to announce the formation of the HSA Foundation that will help drive a unified, open industry standard architecture for heterogeneous processing, and build a strong heterogeneous compute ecosystem for the embedded, mobile and cloud computing markets.
Arteris has also joined the HSA Foundation as a Supporter member and will be actively involved in numerous working groups. Arteris joins the HSA Foundation to bring to realization its vision of true “plug-and-play” heterogeneous IP core integration on systems-on-chip (SoCs). This will finally enable hardware designers to provide software developers the flexibility to make coordinated optimizations for speed, power consumption, and cost. For more information on the HSA Foundation, go to www.hsafoundation.com.
The course DSP Theory, Algorithms and Architectures will take place in Munich, Germany on November 6 to 8, 2012. The syllabus of this three day training spans from the basics of signal processing and the generic DSP system via frequency domain analysis, digital filtering, DSP software/hardware, DSP audio/baseband processing, signal (audio) source coding, adaptive DSP algorithms, computationally efficient DSP linear systems, digital communications, DSP for mobile and wireless down to DSP (software) enabled radio architectures and DSP on FPGAs. The complex mathematical theory associated with digital signal processing is presented in an intuitive and straightforward style. The following prior experience is useful but not essential: programming principles, electrical engineering principles, Bachelor level mathematics. The instruction language is English. More information is available at http://www.hightech-events.com/event/2/Digital-Signal-Processing
Cadence has announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property (IP) family have been proven in silicon on TSMC's 28HPM and 28HP process technologies. Cadence has received and characterized multiple versions of its DDR PHY and controller IP in 28nm silicon based on advanced drafts of the DDR4 standard. The proposed DDR4 standard, anticipated to be released by JEDEC later this year, will offer users substantial performance benefits over DDR3. DRAM devices adopting the DDR4 standard are expected to have 50 percent higher operational frequency and double the memory capacity of DDR3 devices while reducing the power consumed in the DRAM by as much as 40 percent per bit transferred.
Synopsys intends to incorporate on-chip variation (OCV) extensions in its open-source Liberty™ library format, the modeling standard for integrated circuit (IC) implementation and signoff. The new extensions will help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm processes nodes. The final format extensions and ratification as part of the Liberty standard will be completed with the guidance and assistance of the Liberty Technical Advisory Board.
Sand 9 has announced that Ericsson has invested $3 million in the company. Timing devices provide the ‘heartbeat’ for all electronic applications, which include wireline communications infrastructure and cellular base stations, as well as mobile and wireless applications. Sand 9’s micro-electromechanical systems (MEMS) timing products offer significant advantages over legacy quartz crystal solutions, which currently dominate this market. Sand 9’s timing products offer greater immunity to electromagnetic interference (EMI) and vibration in combination with low noise and high stability, which ensures precision timing—even in ruggedized environments.
Altera has unveiled features planned for its next generation of 20-nm products. Extending the promise of silicon convergence, Altera is offering customers a system-integration platform, combining the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). It includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy® ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Sonics has joined the HSA (Heterogeneous System Architecture) Foundation as a contributor member, collaborating with other major industry leaders to support the parallel computing efforts for next-generation heterogeneous processors. In June at the AMD Fusion Developer Summit, major global technology leaders converged to announce the formation of the HSA Foundation that will help drive a unified, open industry standard architecture for heterogeneous processing, and build a strong heterogeneous compute ecosystem for the embedded, mobile and cloud computing markets.
Arteris has also joined the HSA Foundation as a Supporter member and will be actively involved in numerous working groups. Arteris joins the HSA Foundation to bring to realization its vision of true “plug-and-play” heterogeneous IP core integration on systems-on-chip (SoCs). This will finally enable hardware designers to provide software developers the flexibility to make coordinated optimizations for speed, power consumption, and cost. For more information on the HSA Foundation, go to www.hsafoundation.com.
The course DSP Theory, Algorithms and Architectures will take place in Munich, Germany on November 6 to 8, 2012. The syllabus of this three day training spans from the basics of signal processing and the generic DSP system via frequency domain analysis, digital filtering, DSP software/hardware, DSP audio/baseband processing, signal (audio) source coding, adaptive DSP algorithms, computationally efficient DSP linear systems, digital communications, DSP for mobile and wireless down to DSP (software) enabled radio architectures and DSP on FPGAs. The complex mathematical theory associated with digital signal processing is presented in an intuitive and straightforward style. The following prior experience is useful but not essential: programming principles, electrical engineering principles, Bachelor level mathematics. The instruction language is English. More information is available at http://www.hightech-events.com/event/2/Digital-Signal-Processing
Cadence has announced that the first products in the Cadence DDR4 SDRAM PHY and memory controller design intellectual property (IP) family have been proven in silicon on TSMC's 28HPM and 28HP process technologies. Cadence has received and characterized multiple versions of its DDR PHY and controller IP in 28nm silicon based on advanced drafts of the DDR4 standard. The proposed DDR4 standard, anticipated to be released by JEDEC later this year, will offer users substantial performance benefits over DDR3. DRAM devices adopting the DDR4 standard are expected to have 50 percent higher operational frequency and double the memory capacity of DDR3 devices while reducing the power consumed in the DRAM by as much as 40 percent per bit transferred.
Synopsys intends to incorporate on-chip variation (OCV) extensions in its open-source Liberty™ library format, the modeling standard for integrated circuit (IC) implementation and signoff. The new extensions will help standardize usage of the popular stage-based Advanced OCV (AOCV) modeling approach for 40- and 28-nm processes nodes. The final format extensions and ratification as part of the Liberty standard will be completed with the guidance and assistance of the Liberty Technical Advisory Board.
Sand 9 has announced that Ericsson has invested $3 million in the company. Timing devices provide the ‘heartbeat’ for all electronic applications, which include wireline communications infrastructure and cellular base stations, as well as mobile and wireless applications. Sand 9’s micro-electromechanical systems (MEMS) timing products offer significant advantages over legacy quartz crystal solutions, which currently dominate this market. Sand 9’s timing products offer greater immunity to electromagnetic interference (EMI) and vibration in combination with low noise and high stability, which ensures precision timing—even in ruggedized environments.
Altera has unveiled features planned for its next generation of 20-nm products. Extending the promise of silicon convergence, Altera is offering customers a system-integration platform, combining the hardware programmability of FPGAs with the software flexibility of digital signal processors and microprocessors along with the efficiencies of application-specific hard intellectual property (IP). It includes the integration of 40-Gbps transceiver technology, a next-generation variable-precision digital signal processing (DSP) block architecture that delivers over 5 TFLOPs of IEEE 754 floating-point performance, and heterogeneous 3D ICs that integrate FPGAs with a user-customizable HardCopy® ASIC or a variety of other technologies, including memory, third-party ASICs and optical interfaces through an innovative high-speed interface.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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