EDA Countdown: 4-6

9/11/2012 10:54 AM EDT

Last week, in celebration of my first year looking after the EDA Designline, I started the countdown of the top ten design articles for the week. As a reminder, these were the articles in positions 10 through 7

At 10 - Agile hardware development – nonsense or necessity?

At 9 - Power awareness in RTL design analysis

At 8 - Considerations for writing UPF for a hierarchical flow

At 7 - System-level design of mixed-signal ASICs using Simulink: Efficient transitions to EDA environments

Coming in this week at number 6 is “Energy efficient C code for ARM devices” written by Chris Shore at ARM. Hardware engineers have been in the business of saving energy for longer than software engineers but, increasingly Chris says, it is our job to utilize hardware features to the maximum and then realize even greater savings by writing efficient software.

At number 5 is On-chip ESD protection for High Voltage applications in TSMC BCD technology written by Bart Keppens and K. Verhaege of SOFICS. The purpose of ESD protection is to provide a safe, robust current path while limiting the voltage drop below the critical voltage determined by the circuit to be protected. Today, different protection clamp types are used in the industry, each with significant performance and cost burdens that prevent generic use. This articles looks at them in detail.

At number 4 is ACE’ing the verification of a cache coherent system using UVM written by Peer Mohammed of MindSpeed and Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma and  Satyapriya Acharya of Synopsys.The ACE specification enables system-level cache coherency across clusters of multi-core processors. This article describes how the Universal Verification Methodology (UVM) configuration mechanism can be leveraged to optimize configurability of the sequences.

Nest week, we see who came in the top three positions. Congratulations to all of the authors and thanks for helping me make it a great year.