CEO Spotlight: Ellis Smith, Blue Pearl Software

9/12/2012 10:51 AM EDT

At this year's DAC, I conducted a number of interviews with executives from various EDA companies. Some old, some new, some small and others in what I have been calling the emerging middle class of EDA. While I no longer hold to that thesis, the insights from the executives are still valid. In this interview I talked to Ellis Smith, CEO of Blue Pearl Software.

Blue Pearl Software, Inc. provides products that automate the generation of timing constraints, validate existing timing constraints and check functional design issues at the functional or register transfer level (RTL) of the digital chip design flow.

EDA Designline: You’ve been in the industry for quite a long time with various different companies and what have you. Why Blue Pearl?

Smith: This is the 5^th EDA company I have been CEO for and the first company that I’ve founded. I felt that it was really important to provide automation in a place where there wasn’t very much before. It turns out those parts also are ones that cause designers a lot of problems. This can be for one of two reasons: they try to do things by hand, manually, or they just kind of skip some things that are needed that are important.

We have some very interesting technology that we applied to an area where there wasn’t a lot of automation.  And what we have done is develop a tool, or a suite of tools, that do a number of things. One is we, at a functional level, analyze the design and do complete design analysis, providing checks like linting checks but also functional analysis checks of the RTL, and then we display that information in very meaningful and useable ways. The second thing is that we provide checks for data crossing clock domains. It’s become more and more important as more devices have become battery-powered because people want to turn off different parts of the design during different clock cycles, so that you save power. And then the third thing is, although there are people that do parts of time and constraint generation, the tool set that we have has the most complete generation of Synopsys design constraints automatically, and the most complex constraints.

We have encapsulated all of this technology in a user interface that is very intuitive, very easy to use, and provides something that we call vision verification. What we are doing is providing tools for the average designer, not the expert designer. For example, most of the time, constraints are written by hand by designers that understand the design intent. They can look at the design and say, “These are parts of the design that I can constraint in this way.” But it is all manual, done by people who know the design. The primary reason they do that is to meet timing. And, it’s also one of the biggest causes of iterations in the design cycle. They’ll try some constraints, it’ll meet timing, they will look at their Primetime report to see if passed or failed, they’ll come back and look at those because they know the design, they’ll write some more constraints, and then they do this process.  Not only is it time consuming, it’s very error-prone.

Over the last couple of years, a couple of things have happened. One is that, in the FPGA community, you have FPGA providers that are coming out with much more complex systems, in a sense, like a system on a chip. We have Xilinx coming out with their Virtex 7, their new Vivado tool flow, and also dropping in processor core, like the Zynq 7000. That is changing the game of the capability of FPGAs. Because that game is changing, it’s also changing the requirement for design automation tools. And we have focused on that very specific part of the industry.

EDA Designline:  Is that the same focus that you started with when the company was formed, or has that changed as you’ve been through this evolution process?

Smith: It has changed somewhat. When the company was formed, because of the technology we had, we were initially working with companies that were doing the most complex, high-end designs; companies that were doing 20, 30, 40 million gate designs. At that time we were focusing on that set of customers because we felt that we had technology that would address their needs. But over time, what I saw was, the FPGA market was really going up in complexity. In the past, they didn’t have problems with design analysis including linting, they didn’t have clock domain crossing problems, and they never had constraint issues where you needed to constraint synthesis, but now that is hitting full force. If you’re going to play in that market, what you need is a tool that’s very easy to use, and a tool that’s on Windows. Well, we not only have world-class technology applying our tool suite, but we have probably one, if not the easiest to use tools, certainly in our space of industry, and the only one that’s on Windows. So really we fit that market perfectly.

EDA Designline: Are the problems that they are facing simpler?

Smith: Let me change the question around a little bit. The problems we’re dealing with are not simple. Design complexity of this type is really hitting the FPGA market, and 10 years ago, 5 years ago, 3 years ago, people were not seeing this type of requirement for our type of tools in the FPGA market, now that is coming full stream. So it’s still a complex problem, but we wanted to make a tool that was easy enough to use for the average FPGA designer which may not have the breadth of experience that a very sophisticated ASIC designer would have for example, that would use tools in this space. And I think that ease of use determines how fast you can proliferate within an industry or within an account, and that is very important. If you have to spend months learning a tool, the ins and outs of a tool, and if you have to spend weeks and months integrating it, and then you have to have somebody write a lot of scripts just to get it to work in your environment, and then every time you use it, you have to figure out a way that you can best use this information - that kind of defeats the purpose of design automation.

EDA Designline: Few companies seem to have made it economically in the FPGA market because the average selling prices are so much lower than the ASIC market. What makes you think that you’re going to be different?

Smith: Well, I was the CEO of one of the companies that have made it economically in the FPGA market - Exemplar, and there are other companies, like Simplicity, and a few other ones, that have done very well. But the other thing that is happening is, if you look at where Xilinx and Altera are going with their design complexity and what you can do with their largest devices, that is a market that will do nothing but grow. So we’re focusing on a market where we’re also poised for very big growth – growth in design complexity and device complexity.

EDA Designline: I know this is not going to be the top thing on your mind, the exit strategy for most EDA companies is for one of the big three you to buy you. Do you think that you are courting them or the FPGA companies perhaps?

Smith: I always have the same answer. Build a company that is very valuable to your customers, to the industry, to your employees, and you will be able to realize that value. Exits take care of themselves when you do that. And there are much more than just three EDA companies that could potentially acquire us in the future. Many more, but I won’t go into that right now.

EDA Designline: What is the principle message you’re trying to get out as a company at the moment?

Smith: We have products that are the next generation of EDA products, that combine high value to users in that we’re very easy to evaluate, integrate, and use to get immediate help in areas of the design flow where we provide tools: design analysis, clock domain crossing and automatic generation of timing constraints. It is also very easy for the customer to see that value. And without going into prices, we have very enviable price points. Part of that is due to the company structure, part of it is due to the growth ramp that we are on.