EDA/IP Weekly Roundup – September 19th

9/19/2012 11:11 AM EDT

This is a roundup of news or activities in the past few days that may be of interest to people.

Cadence is hosting its second Mixed-Signal Technology Summit, providing a venue for customers and partners to learn about and discuss the latest technologies and methodologies for mixed-signal design. Professor Ali Niknejad, University of California at Berkeley, will deliver an academic keynote, and Chris Collins, director, Analog EDA and Design Services at Texas Instruments, will deliver an industry keynote. There is no fee to attend. Sept. 20, 2012. Free copies of the recently released Mixed-Signal Methodology Guide will be available at the social hour.

Synopsys has announced an expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the emerging DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets. The solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns.

EVE has announced the e-zTest MIPI CSI-2 and e-zTest MIPI DSI validation platforms. These two new wireless system-on-chip (SoC) validation platforms support the Mobile Industry Processor Interface (MIPI) Alliance wireless standards for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI). They allow fast configuration of virtual cameras and virtual displays, along with an interface to a DUT in the ZeBu SoC emulation system. The virtual test environment offers network accessibility of the design to any hardware or software engineer.

Kilopass Technology is talking about its new embedded VCM (Vertical Cross-point Memory) NVM IP bit cell. The new VCM bit cell quadruples the density of today’s anti-fuse NVM IP bit cell. The VCM bit cell will make possible program storage where today’s embedded non-volatile memory (eNVM) technology is cost-prohibitive or unavailable at capacities of 4Mb to 32Mb. It will also enable a higher level of performance more similar to SRAM compared to existing slower eNVM technologies or external flash or EEPROM chips.

Aldec has announced HES-7, a scalable ASIC prototype system. HES-7 takes advantage of the Xilinx® Virtex-7 2000T 3D IC, which enables design capacity up to 24 million ASIC gates on a single HES-7 board. HES-7 utilizes a non-proprietary high-speed backplane connector that enables easy expansion of custom daughter boards or can enable up to four (4) HES-7 boards to interconnect - which provides design capacity up to 96 million ASIC gates. Pricing that starts at $19,995.00.

Digital Core Design has been nominated for the European Business Award and is the only IP Core and SoC design house in the running. They are asking everyone to vote for DCD. If you wish to support them go to the official web site:  http://www.businessawardseurope.com/entries/detail/Poland/4683 and vote for the DQ80251, the world’s fastest 8051 CPU.

Sisvel says that it has been coordinating meetings among owners of patents essential to the DVB-C2 standard for the purpose of creating a patent pool to offer licenses under their combined portfolio of patents to make DVB-C2 technology accessible to all users on fair, reasonable, and non-discriminatory terms and conditions. The companies participating in Sisvel’s effort are: DTVG Licensing, France Telecom, TDF, LG Electronics, and Radiotelevisione Italiana (RAI).

Semiconductor Manufacturing International Corporation (SMIC) has announced the availability of its 1.2-volt Low-Power Embedded EEPROM Platform, which is fully compatible with its 0.13-micron (um) low-leakage (LL) process. The process- and IP-qualified platform is designed to reduce power consumption, chip size, and cost, while increasing data security. The new platform is SMIC's latest offering for mature process nodes and is targeted at China's fast-growing dual-interface financial IC card market, as well as the worldwide market for contactless smart cards.

The market for integrated circuits is forecast to post much stronger average annual growth through 2021 compared to the average market growth over the past 15 years, according to an analysis recently completed by IC Insights. Though IC unit growth is expected to slow, the IC average selling price (ASP) is expected to jump into the positive range, and help boost average annual IC market growth to 8.0% per year from 2011-2021, an increase of 54% compared to the 5.2% annual growth the IC market averaged in the period between 1996 and 2011.