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LVS Debug: The Good, The Bad, and The Future
Srinivas Velivala, Mentor Graphics
9/25/2012 1:31 PM EDT
Comparison errors
Comparison errors
Non-texted shorts
In addition to the texted shorts that are caught as part of the extraction process, there are non-texted shorts generated during the comparison process. Non-texted shorts are actual connectivity issues that have been analyzed and found to be a short by the comparison process. Once all of the texted shorts have been corrected, designers can begin debugging these comparison errors, which can sometimes be tricky to correct.
To help them fix non-texted shorts, designers can use Calibre RVE to see a visual representation of the layout and source netlists used in the LVS run, and debug LVS discrepancies by comparing the source and layout schematics side-by-side. These schematics are especially valuable to designers when schematics are not otherwise available for debug (e.g., Verilog).
To debug a non-texted short present in the layout, designers work from the source netlist information, which is considered the “golden” data. They can separately highlight the instances on the source nets corresponding to the shorted layout net, using different colors to trace the good segments to find the bad one. Color consistency of highlighted layers between the external design environment and Calibre RVE schematics ensures users can easily identify the nets and devices highlighted when cross-probing.
In our example, the shorted layout net 13 is made up of two nets, n3 and n1, in the source (Figure 5). The instances on the two source nets (n3, n1) are separately highlighted.
A cross-connect error is a common LVS discrepancy that is caused by swapped signal nets in the layout. Our example contains a typical case of swapped signals, as the counts of Nets and Instances for the design cell matches in both layout and source netlists, but the count for the Ports is different, indicating that this is a connection problem (Figure 7). To help reduce debugging time, Calibre RVE provides users with a “fix suggestion” that contains a simple English language description of the problem. In our example, this description tells us that there is a cross-connect error between layout nets 10 and 5 due to a faulty wiring connection, and that swapping the connections for the two nets will fix the problem.
LVS debug of today’s complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers. As the chip industry moves towards advanced technology nodes, design automation technology must ensure that it provides the speed and quality of results necessary to ensure the continued success of its customers. EDA vendors are providing new techniques and tools that work together to automated and enhance LVS debugging capabilities, ensuring that their customers can meet market deadlines while maintaining product quality, even for the most advanced designs.
About the author
Srinivas
Velivala is a Technical Marketing Engineer with the Design to Silicon
Division of Mentor Graphics, focusing on developing Calibre integration
and interface technologies. Before joining Mentor, he was an IC
designer, designing high density SRAM compilers. Srinivas received a
B.tech. in Electronics from Jawaharlal Nehru Technological University in
Hyderabad, India, and pursued additional studies at Southern Illinois
University in Carbondale, Illinois. He can be reached at
srinivas_velivala@mentor.com .
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Comparison errors
Non-texted shorts
In addition to the texted shorts that are caught as part of the extraction process, there are non-texted shorts generated during the comparison process. Non-texted shorts are actual connectivity issues that have been analyzed and found to be a short by the comparison process. Once all of the texted shorts have been corrected, designers can begin debugging these comparison errors, which can sometimes be tricky to correct.
To help them fix non-texted shorts, designers can use Calibre RVE to see a visual representation of the layout and source netlists used in the LVS run, and debug LVS discrepancies by comparing the source and layout schematics side-by-side. These schematics are especially valuable to designers when schematics are not otherwise available for debug (e.g., Verilog).
To debug a non-texted short present in the layout, designers work from the source netlist information, which is considered the “golden” data. They can separately highlight the instances on the source nets corresponding to the shorted layout net, using different colors to trace the good segments to find the bad one. Color consistency of highlighted layers between the external design environment and Calibre RVE schematics ensures users can easily identify the nets and devices highlighted when cross-probing.
In our example, the shorted layout net 13 is made up of two nets, n3 and n1, in the source (Figure 5). The instances on the two source nets (n3, n1) are separately highlighted.
Figure
5: Non-texted layout shorted net 13 is shown highlighted in the Calibre
DesignRev environment. The corresponding two source nets, n1 and n3,
are highlighted in the Calibre RVE source netlist schematic.
By
highlighting the known devices in the source netlist, designers can
visually prune the non-shorted portion of the net to reduce the problem
to the remaining portion on the net (Figure 6).Figure
6: The devices corresponding to source nets n1 and n3 are highlighted
separately in the Calibre RVE source schematic, and the corresponding
layout net is shown. Users can visually inspect the shorted layout net
and the corresponding source nets to deduce the location of the short.
Cross-Connect ErrorsA cross-connect error is a common LVS discrepancy that is caused by swapped signal nets in the layout. Our example contains a typical case of swapped signals, as the counts of Nets and Instances for the design cell matches in both layout and source netlists, but the count for the Ports is different, indicating that this is a connection problem (Figure 7). To help reduce debugging time, Calibre RVE provides users with a “fix suggestion” that contains a simple English language description of the problem. In our example, this description tells us that there is a cross-connect error between layout nets 10 and 5 due to a faulty wiring connection, and that swapping the connections for the two nets will fix the problem.
Figure
7: A simple English language description of the LVS cross-connect
error. Count of the Nets, Instances and Ports for the design cell in
both Layout and Source netlist cells is displayed. The mismatch in the
count of Ports indicates a connection problem.
To debug
this problem, designers can use the fix suggestion to highlight the two
nets and instances that have a cross-connect error in the layout
environment (Figure 8). From the highlights, it is easy for the
designers to see that there are swapped signal connections between the
two nets. To fix this problem, the designers just need to swap the via
connections between the two nets (Figure 9).Figure 8: Highlights of Nets 10 and 5 cross-connected to instances M7 and X27/M0 respectively
Figure 9: Swapping the via-connections between the two nets fixes the cross-connect error.
ConclusionLVS debug of today’s complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers. As the chip industry moves towards advanced technology nodes, design automation technology must ensure that it provides the speed and quality of results necessary to ensure the continued success of its customers. EDA vendors are providing new techniques and tools that work together to automated and enhance LVS debugging capabilities, ensuring that their customers can meet market deadlines while maintaining product quality, even for the most advanced designs.
About the author
Srinivas
Velivala is a Technical Marketing Engineer with the Design to Silicon
Division of Mentor Graphics, focusing on developing Calibre integration
and interface technologies. Before joining Mentor, he was an IC
designer, designing high density SRAM compilers. Srinivas received a
B.tech. in Electronics from Jawaharlal Nehru Technological University in
Hyderabad, India, and pursued additional studies at Southern Illinois
University in Carbondale, Illinois. He can be reached at
srinivas_velivala@mentor.com .If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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