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Startup Profile: ProPlus Design Solutions
Brian Bailey
10/4/2012 3:20 PM EDT
Zhihong Liu is the executive chairman of ProPlus Design Solutions, a company that he and several of his colleagues from Cadence started in late 2006. They acquired the device modeling product lines from Cadence, including the advanced device modeling extraction tools BSIMProPlus and NoisePro, and an advanced device modeling services lab. The product line has a long lineage, starting its history in 1995 within Berkeley Technology Associates (BTA) which was acquired by Celestry in 1996, then by Cadence in 2002 and now the tradition continues at ProPlus. While this business was not large enough to be considered important to Cadence, it clearly provided a good financial base for a startup.
These tools have served as the de-facto golden solution for leading semiconductor companies worldwide including foundries, IDMs and fables companies over the past 2 decades. They have over 100 customers for these tools.
Zhihong Liu says that since I joined the company, I have tried to restructure it and step out of the single tool and technology type of company and turn it into a solution provider. That solution is Design for Yield (DFY) and we want to integrate all the key components, including device modeling software, a parallel Spice engine and statistical analysis algorithms so that they can be obtained from a single vendor.
TSMC has been using BSIMProPlus for over 15 years now and they count on this technology to provide their customers with SPICE models. We have been extending this technology to provide statistical models which are based on circuit performance. Part of the problem is that existing models are based on the concept of stronger and weaker transistors but this is based on a digital concept and not an analog concept. So they create fast corner and slow corner but many people want to know about the analog behavior and things such as gm/ID, the ratio of transconductance to dc drain current which is crucial to low power design.
The team has also developed a simulator tuned for statistical analysis. Simulators today just do transient simulation and then you provide thousands of seeds for Monte Carlo analysis. But the simulator was not built natively to run statistical analysis. We do that natively so the construction of the simulator is different. This provides a significant performance gain compared to more traditional simulator design for statistical analysis. Also, when doing DFY types of analysis, the circuits tend to be small and traditional acceleration techniques do not apply to these circuits.
Multi variance analysis is different from Monte Carlo. For a memory type of design you may have to run millions of runs for a cell which is only 6 transistors for an SRAM cell and each run may take just 5 seconds. For high sigma, high yield, you may need to run orders of magnitude more cases. We decided to partner with IBM to actually perform the high sigma analysis. IBM has been using this technology the last seven years and they have lots of hardware measurements so it is completely proven and this can significantly reduce the number of cases that have to be run.
As devices get more advanced, the variations get more complex so the design community is looking for better solutions. Local variation is a statistical problem that impacts the return of using new technologies. To improve it, a tool is required to use as much information as possible and help the design make the design less sensitive to these random variations. This is different from the processes corners that affect the entire chip. This has become important from 65nm down and most foundries now provide these statistical models.
NanoYield was introduced recently and we have our first customer engagements going on now. This includes a tightly integrated NanoSpice.
The company is self-funded with a few angel investors. We have almost the complete Celestry team working on this problem now and have been together for many years. We have a product line that is well established and the company is self-sufficient and profitable. The company has been profitable ever since we paid off the Cadence purchase.
We have grown from 10 persons to almost 100 people today. Most of the engineering is performed in China (70%) but the advanced R&D is performed in the US along with the company headquarters.
More information can be found on their website.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
These tools have served as the de-facto golden solution for leading semiconductor companies worldwide including foundries, IDMs and fables companies over the past 2 decades. They have over 100 customers for these tools.
Zhihong Liu says that since I joined the company, I have tried to restructure it and step out of the single tool and technology type of company and turn it into a solution provider. That solution is Design for Yield (DFY) and we want to integrate all the key components, including device modeling software, a parallel Spice engine and statistical analysis algorithms so that they can be obtained from a single vendor.
TSMC has been using BSIMProPlus for over 15 years now and they count on this technology to provide their customers with SPICE models. We have been extending this technology to provide statistical models which are based on circuit performance. Part of the problem is that existing models are based on the concept of stronger and weaker transistors but this is based on a digital concept and not an analog concept. So they create fast corner and slow corner but many people want to know about the analog behavior and things such as gm/ID, the ratio of transconductance to dc drain current which is crucial to low power design.
The team has also developed a simulator tuned for statistical analysis. Simulators today just do transient simulation and then you provide thousands of seeds for Monte Carlo analysis. But the simulator was not built natively to run statistical analysis. We do that natively so the construction of the simulator is different. This provides a significant performance gain compared to more traditional simulator design for statistical analysis. Also, when doing DFY types of analysis, the circuits tend to be small and traditional acceleration techniques do not apply to these circuits.
Multi variance analysis is different from Monte Carlo. For a memory type of design you may have to run millions of runs for a cell which is only 6 transistors for an SRAM cell and each run may take just 5 seconds. For high sigma, high yield, you may need to run orders of magnitude more cases. We decided to partner with IBM to actually perform the high sigma analysis. IBM has been using this technology the last seven years and they have lots of hardware measurements so it is completely proven and this can significantly reduce the number of cases that have to be run.
As devices get more advanced, the variations get more complex so the design community is looking for better solutions. Local variation is a statistical problem that impacts the return of using new technologies. To improve it, a tool is required to use as much information as possible and help the design make the design less sensitive to these random variations. This is different from the processes corners that affect the entire chip. This has become important from 65nm down and most foundries now provide these statistical models.
NanoYield was introduced recently and we have our first customer engagements going on now. This includes a tightly integrated NanoSpice.
The company is self-funded with a few angel investors. We have almost the complete Celestry team working on this problem now and have been together for many years. We have a product line that is well established and the company is self-sufficient and profitable. The company has been profitable ever since we paid off the Cadence purchase.
We have grown from 10 persons to almost 100 people today. Most of the engineering is performed in China (70%) but the advanced R&D is performed in the US along with the company headquarters.
More information can be found on their website.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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