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eastlau

1/24/2013 8:33 AM EST

Good!

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Steve Schulz

10/23/2012 5:19 PM EDT

Thanks for the compliment -- and for catching my creative re-labeling of the ...

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Collaborative Advantage: Silicon photonics is hot -- at Si2

Steve Schulz

10/17/2012 10:10 PM EDT

Last week’s EE Times article by Rick Merritt (“Silicon photonics is hot, OpenFlow is not”, Oct. 11th ) brought into wider public view an emerging area of technology that had long been a dream: integrating optical routing and switching into silicon chips.  It’s been a favorite dream of mine since my many years at TI, where I lobbied for an investment strategy because I recognized the potential value (if not any near-term means to achieve it).  The benefits are huge – three orders of magnitude improved communications bandwidth, lower power consumption, EM / noise immunity, just to name a few.

Photonics is not brand new.  However, shrinking the feature sizes down to silicon dimensions remains an active area of research.  It is no small feat to manufacture waveguides, effervescent coupling rings, and laser diodes embedded in silicon.  There are complex issues that begin with basic laws of physics and materials science that can impact today’s semiconductor manufacturing processes.  However, the production design and verification of these photonic silicon devices is largely an unsolved problem, with commercial software vendors providing focused capability but lacking good integration into current-day manufacturing flows.  There is no photonics-aware PDK (process design kit) to hand off from a foundry for use in a full silicon design flow, and DRC / DFM rules to verify the physical layout of photonics devices are still an active area of research.

Yet, even if all those advances allow a reliable commercial silicon photonics capability, it means little if the photonic features cannot be integrated with the existing microelectronics industry.  Photonics must leverage the large existing electronics design / foundry infrastructure, and therefore must support true co-design and co-verification.  It is essential to build upon open standards in order to exchange the detailed data necessary for design tools to manage both aspects of co-design.



However, this issue is still more complex because many of the expected commercial adoption scenarios for photonics will also need to utilize 2.5D / 3D technology.  So, we not only need to understand the nature of photonics data to be exchanged and how to best represent it alongside electronics data objects, but we also need to support 2.5 / 3D simultaneously.  All of these definitions inherently require open standards for the diverse community to cooperate and develop an infrastructure layer that can support the competitive open market to come.

DARPA has funded U.S.-based silicon photonics research for years, as has the European Commission (EC).  The EC funded HELIOS project has released several proof-of-concepts including advancement in silicon lasers.  One of the results from this project has been the establishment of a photonics design flow modeled after the electronics design flow.  Recently, the EC approved a 4-year contract involving 15 European entities called “Plat4M”, which seeks to prove the ability to design and manufacture silicon photonics in several vertical market segments, and in so doing lay the groundwork for the necessary commercial infrastructure.  The Plat4M partners are committed to using OpenAccess as the foundation for their co-design flows, which necessitates adding photonics extensions to the data model, API, and software reference implementation.  As such, Si2 was requested to serve as a partner to define and develop these extensions, all of which will become available to Si2 members and the entire industry, as is our tradition.

Furthermore, the Plat4M collaborative project will also explore the usage of OpenDFM and OpenPDK to support interoperable, intent-based DRC / DFM and PDK capabilities, with firm decisions to be made in the first half of the project.  All three Si2 standards – OpenAccess, OpenDFM, and OpenPDK – will require close collaborative research with all Plat4M partners, and the research extensions must not disrupt stability or performance of their preexisting electronics features.

Si2 has chosen to create a new Technical Advisory Board to manage the collection and documentation of industry requirements, definition of extensions, and distribution of pre-commercial software supporting these industry goals.  The Silicon Photonics TAB (SP TAB) was approved by Si2’s Board of Directors, and officially begins, this month, to extend OpenAccess by enabling photonics / electronics co-design for the industry’s future.  More details will be coming shortly in a full press announcement and additional blogs.  However, you may also visit our SP TAB introduction page.

Other recent Collaborative Advantage blogs
Collaborative Advantage: Celebrating Ten years of OpenAccess!
Collaborative advantage: The future of fabless design?
Collaborative Advantage: How Apple-Samsung will impact standards development



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BrianBailey

10/18/2012 5:11 PM EDT

Steve, we rarely get to the end goal in one step so it would seem reasonable that there are sub goals that could be defined with photonics. If this is true, what is the first way in which we could actually see them being used - chip to chip communications perhaps?

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Steve Schulz

10/18/2012 6:12 PM EDT

Brian - there are indeed a number of "sub-goals" on the path to photonics nirvana, and many are laid out in detailed pre-competitive R&D plans by Plat4M, DARPA, etc. Nothing makes sense until you can reliably manufacture an embedded waveguide that keeps the light inside, so industry needs to decide what materials and mfg process technologies work just for the photonics side. After that, then there are choices for what form the larger integration takes - I think it likely that waveguides and coupling rings may be on their own silicon (say, 90nm SOI), with the complex electronics on standard bulk CMOS die. In that scenario, you only need to deal with the laser diodes in CMOS... but then you need 2.5D or 3D stacking on an SOI interposer where hi-bandwidth chip-chip communications could take place. Later, more might migrate alongside transistors on the same die or in a true 3D stack. Then again, I'm not an expert here -- Si2 is learning rapidly as we engage to enable their needs in Si2 standards (hmm... not a bad reason for folks to join the SP TAB!).

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A Benner

10/21/2012 6:31 AM EDT

A nit:
"effervescent coupling" should be "evanescent coupling"

Nice article.

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Steve Schulz

10/23/2012 5:19 PM EDT

Thanks for the compliment -- and for catching my creative re-labeling of the evanescent coupling effect! Now I know what I can expect when I rush a blog on my way to the airport...

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eastlau

1/24/2013 8:33 AM EST

Good!

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