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NEMS eyed for CMOS power gating
Brian Bailey
10/25/2012 2:18 PM EDT
The steady rise in leakage power over the last decade has made low-power design an exceedingly difficult problem mainly because attempts to control leakage power tend to negatively impact performance and switching energy. For devices with long idle periods that are leakage-dominant, power gating has emerged as a popular technique for combating idle leakage.
The industry standard approach for power gating with on-die transistors has major drawbacks including residual off-state leakage, which still forces designers to resort to leakage control measures such as high threshold voltages. Leyla Nazhandali Center for Embedded Systems for Critical Applications (CESCA) member and Masoud Agah (director of VTMEMS Lab) are attempting to solve this dilemma by using NanoElectroMechanical Systems (NEMS) switches. Their recently NSF funded project intends to investigate all aspects of CMOS-NEMS integration. NEMS switches will be designed and developed that are specially targeted for effective power gating. The on-chip control circuitry will also be developed and tested, which includes a high-voltage generation system and a self-healing controller that can gracefully handle switch failure. Furthermore, 3D integration techniques will be evaluated for the integration of the NEMS switches with the CMOS die in such a way that power-network resistance and capacitance is minimized. The final product is a fabricated CMOS-NEMS hybrid that would allow us to conclusively determine the effectiveness of NEMS-based power gating.
More information about this grant can be found here
Questions should be sent Leyla Nazhandali (leyla@vt.edu).
If you would like to have your research featured here, please send me an email and I will let you know if I think it is appropriate for this audience.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
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The industry standard approach for power gating with on-die transistors has major drawbacks including residual off-state leakage, which still forces designers to resort to leakage control measures such as high threshold voltages. Leyla Nazhandali Center for Embedded Systems for Critical Applications (CESCA) member and Masoud Agah (director of VTMEMS Lab) are attempting to solve this dilemma by using NanoElectroMechanical Systems (NEMS) switches. Their recently NSF funded project intends to investigate all aspects of CMOS-NEMS integration. NEMS switches will be designed and developed that are specially targeted for effective power gating. The on-chip control circuitry will also be developed and tested, which includes a high-voltage generation system and a self-healing controller that can gracefully handle switch failure. Furthermore, 3D integration techniques will be evaluated for the integration of the NEMS switches with the CMOS die in such a way that power-network resistance and capacitance is minimized. The final product is a fabricated CMOS-NEMS hybrid that would allow us to conclusively determine the effectiveness of NEMS-based power gating.
Questions should be sent Leyla Nazhandali (leyla@vt.edu).
If you would like to have your research featured here, please send me an email and I will let you know if I think it is appropriate for this audience.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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