EDA/IP weekly roundup – November 7th

11/7/2012 10:35 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Mentor Graphics has announced hardware and software solutions to accelerate the verification of PCI Express Generation 3 products. These new solutions, when connected to a Veloce® emulator, enable designers to test the new generation PCI Express devices on their System-on-Chip (SoC) designs, and to develop and test their software drivers and firmware prior to silicon being available. The Gen3 product is also fully compatible with older Gen1 and Gen2 speed devices.

The Global Semiconductor Alliance (GSA) and its Capital-Lite Working Group, whose primary focus is to help semiconductor startups improve their chance of success by providing new business models, partnerships and tools, published “A Startup’s Guide to Surviving an Investment Drought.” The white paper focuses on invigorating semiconductor startups to enable high quality innovation, increased investment and subsequent returns, and stimulate sustainable M&A, as well as new IPOs. For more about this see Chip group says business model must evolve.

Altera has announced a new Serial RapidIO® Gen2 MegaCore® function IP. The new IP solution has successfully completed full hardware interoperability with the latest RapidIO switch from Integrated Device Technology (IDT),operating at 6.25 Gbaud per lane implemented on a 28 nm Altera Stratix® V FPGA.

Atrenta and TSMC announced the planned availability of IP Kit 2.0. Based on the SpyGlass® RTL design platform, IP Kit is a fundamental element of TSMC’s soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft, or synthesizable IP. IP Kit 2.0 has undergone extensive beta testing by TSMC soft IP alliance partners: Digital Media Professionals Inc., Dolphin Integration, Sonics, Inc. and Vivante Corporation. IP Kit 2.0 will be fully supported on TSMC-Online and available to all TSMC’s soft IP alliance partners on Nov. 20, 2012.

Weightless is a global organization delivering royalty-free open standards to enable the Internet of Things and has announced a new Special Interest Group (SIG) to accelerate the adoption of “Weightless” as a wireless wide area global standard for machine to machine (M2M) short to mid-range communications. The group plans for completion in early 2013.

Agilent has a new 802.11ac WLAN test solution. The latest WLAN technology, 802.11ac, builds on 802.11n with a wider RF bandwidth (up to 160 MHz), MIMO support and high-density 256-QAM modulation to enable 1-Gbps throughput below 6 GHz for multiple stations. Agilent’s X-Series signal analyzers now support this emerging standard with the release of the two new options for the N9077A WLAN measurement application that simplify design verification and speed high-volume manufacturing.

X-FAB Silicon Foundries has increased its stake in the MEMS Foundry Itzehoe GmbH (MFI) from 25.5 percent to 51 percent – becoming the majority shareholder – and also renamed MFI as X-FAB MEMS Foundry Itzehoe.  The Itzehoe site complements the MEMS capabilities and resources of the recently announced X-FAB MEMS Foundry in Erfurt, adding technologies for micro sensors, actuators, micro-optical structures and hermetic wafer-level packaging processes.

Novarm, a developer of PCB design software has announced DipTrace 2.3. This updated version features online design rules check, VRML 2.0 3D export, custom non-signal layers as well as advances in hierarchy, file compatibility, working speed and much more. DipTrace 2.3 is aimed at small and medium businesses. DipTrace is bundled with four modules, Schematic, PCB Layout with shape-based autorouter, Pattern Editor and Component Editor.

Macnica has released a 20G serial ethernet compatible chip-to-chip and backplane communications IP for FPGA. The 20G serial chip-to-chip communication module is a small, easy to implement design allowing high-speed data transfer over 3 lanes running at 6.375Gbps on Altera FPGAs. The design uses 17k LEs.

Mentor Graphics has a new Tessent® IJTAG solution, which allows designers to reuse test, monitoring and debugging logic embedded in existing IP blocks. Supporting the IEEE P1687 (IJTAG) standard, the solution automatically retargets test and debug commands and generates an integrated hierarchical control and data network with a single top-level interface for an entire SoC. The solution, which supports any embedded instrumentation compliant to the P1687 standard, can be used where pin count is limited or access is difficult, as in stacked die configurations.

X-FAB Silicon Foundries and non-volatile memory specialist Anvo-Systems Dresden today announced a cooperative agreement to offer high-speed non-volatile memory solutions that combine SRAM, DRAM and SONOS FLASH technologies. In this partnership, Anvo-Systems Dresden provides the IP and design expertise, and X-FAB provides the semiconductor manufacturing process, capacity and quality assurance. The new nvSRAM solutions are ideal for solutions requiring high reliability and security, such as for medical, communication, automotive, bio-technology and industrial control and metering applications.

Synopsys has updated its DesignWare® STAR Memory System®. The latest release, targeting 20-nm- and FinFET-based designs, includes a new architecture enabling hierarchical implementation and validation of large SoC designs containing thousands of embedded memories. In addition, the new release addresses test and repair for new memory defects seen in 20-nm processes and below such as process variation faults and resistive faults.

Aldec has announced the release of its mixed language advanced verification platform, Riviera-PRO™ 2012.10. The release delivers numerous stability and performance improvements, support for the latest versions of industry-standard SystemVerilog verification libraries, new language constructs, new debugging tools, and improved interfaces to other industry-leading EDA tools. Riviera-PRO delivers a 20% VHDL simulation performance gain over previous releases.

Databeans expects that the global high performance analog market will reach $12.9 billion this year, a 2 percent increase from 2011, and will grow at an estimated CAGR of 10 percent annually over the next five years. High performance analog includes any analog product, such as data converters, amplifiers, interface, etc. that are high speed, precision, or based on any specification where performance is valued above price.

JEDEC Solid State Technology Association and the Open NAND Flash Interface Workgroup (ONFI) have announced the publication of JESD230 NAND Flash Interface Interoperability Standard (Package). This jointly developed document defines a standard for NAND flash device interface interoperability. JESD230 is available for free download from both www.jedec.org and www.onfi.org. JESD230 addresses signaling descriptions, packages, definitions, abbreviations and conventions, and is backwards compatible with existing technologies to the greatest degree possible. The standard will help enable the design of interoperable systems that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices.

Silicon Laboratories has introduced a digital relative humidity (RH) and temperature “sensor-on-a-chip” solution. The new Si7005 sensor combines a mixed-signal IC manufactured on standard CMOS with a technique of measuring humidity using a polymer dielectric film. Traditional approaches to RH sensing use discrete resistive and capacitive sensors, hybrids and multi-chip modules (MCMs). Temperature is sensed by a precision bandgap referenced circuit on the die. Humidity is sensed by measuring the capacitance change of an industry-standard low-k dielectric layer applied to the surface of the die.