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Udi.Barzilai
I honestly don't see the point in measuring the distribution of _die_area_ ...
Myths, hype and the building blocks of SoCs
Brian Bailey
11/8/2012 6:21 PM EST
I was on a product introduction call the other with some of the folks at Synopsys and they put up a slide that showed the amounts of reuse in a typical chip. This was not central to the main discussion, but it struck me as being out of whack with conventional messaging I have been hearing about for the past decade or more about IP, reuse and design costs. Here is the chart from that presentation.
The source cited was Semico from June 2010. I looked at the bar for 2011 (not much of a projection) and was surprised by two things – reuse only accounted for 20 percent of the chip and that figure was decreasing, although at a slower rate than the decrease in new logic. I have heard so many people talk about a chip being 90 percent reuse and even if we count the memory as reuse, that only gives 80 percent and even by 2017 it is not expected to be 90 percent. So what is the reality?
First, here is the latest graph and data from Semico dated 11/12
First, we see that for 2011 that 90 percent was indeed the point we attained if memory is included and that memory has recently taken a big jump from 58 percent to 73 percent in a single year! Also the other observation is still intact: IP reuse area is declining but at a slower rate than new logic.
I want to thank both Synopsys and Rich Wawrzyniak of Semico for their responses which are provided below.
Next: Semico response
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Udi.Barzilai
11/20/2012 9:37 AM EST
I honestly don't see the point in measuring the distribution of _die_area_ between new/reused design and memory.
Die area may influence cost models, yields etc but has little bearing on the design realted aspects of a chip.
One can fill 90% of a chip with replicated memory banks, using almost no design effort. Memory doesn't need to be functionally or formally verified. Doesn't need to be timing-closed. Doesn't need gate-level simulations. Integration of memory into a design is normally straightforward.
Memory should simply be left out of any discussion regarding "innovation in hardware being constrained".
Memory aside, we are left with new vs. reused blocks. Even here die area is of little value in the discussion, since if I have 12 hardened CPU cores replicated in my design, they may dominate the die area and still be a negligible part of the project when measured in design effort (= schedule, = investment, ~ innovation).
Just removing memories from the graphs in the article will show that while there is a clear increase in the die area share of reused designs, it is not a sharp exponential trend and the ratio just transitioned from ~40:60 to ~60:40 over 2 decades. This is by no means a _fundamental_ change of the industry.
Keeping in mind that due to replication, die area is at best an "inaccurate" indicator of design effort / innovation, I don't think any serious conclusion can be drawn about the subject purely from die-area data.
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